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arXiv · 2505.18353

Current-Steering DAC Architecture Design for Amplitude Mismatch Error Minimization

Ramin Babaee·Shahab Oveis Gharan·Martin Bouchard
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Abstract

We propose a novel digital-to-analog converter (DAC) weighting architecture that statistically minimizes the distortion caused by random current mismatches. Unlike binary, thermometer-coded, and segmented DACs, the current weights of the proposed architecture are not an integer power of 2 or any other integer number. We present a heuristic algorithm for a static mapping of DAC input codewords into corresponding DAC switches. High-level Matlab simulations are performed to illustrate the static performance improvement over the segmented structure.

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Ramin Babaee, Shahab Oveis Gharan, Martin Bouchard. 2025-05-23. Current-Steering DAC Architecture Design for Amplitude Mismatch Error Minimization. https://doi.org/10.1109/iscas58744.2024.10558417

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