Experimental realization of all logic elements and memory latch in SC-CNN Chua's circuit

Ashokkumar P; Sathish Aravindh M; Venkatesan A; Lakshmanan M

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arXiv · 2505.23303

Experimental realization of all logic elements and memory latch in SC-CNN Chua's circuit

Ashokkumar P·Sathish Aravindh M·Venkatesan A·Lakshmanan M

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Abstract

The Chua's circuit is examined using a State Controlled-Cellular Neural Network (SC-CNN) framework with two logical square wave input signals. We illustrate, in particular, that this nonlinear circuit can generate all the basic logic operations, including OR/NOR, AND/NAND, and XOR/XNOR gates, by making use of the hopping of attractors which this circuit produces in different phase space regimes. Further, it is shown that besides two-inputs, the circuit emulates multi-input logic elements. Moreover, all these logic elements are effectively functioning for a tolerable limit of noise intensity. These observations are experimentally realized. Thus our investigation sheds new light in the field of digital technology where the existing static logic gates may be replaced or complemented by this kind of dynamical nonlinear circuits.

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Ashokkumar P, Sathish Aravindh M, Venkatesan A, Lakshmanan M. 2025-05-29. Experimental realization of all logic elements and memory latch in SC-CNN Chua's circuit. https://arxiv.org/abs/2505.23303

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