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arXiv · 2506.15613

From Block to Byte: Transforming PCIe SSDs with CXL Memory Protocol and Instruction Annotation

Miryeong Kwon·Donghyun Gouk·Junhyeok Jang·Jinwoo Baek·Hyunwoo You·Sangyoon Ji·Hongjoo Jung·Junseok Moon·Seungkwan Kang·Seungjun Lee·Myoungsoo Jung
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Abstract

This paper explores how Compute Express Link (CXL) can transform PCIe-based block storage into a scalable, byte-addressable working memory. We address the challenges of adapting block storage to CXL's memory-centric model by emphasizing cacheability as a key enabler and advocating for Type 3 endpoint devices, referred to as CXL-SSDs. To validate our approach, we prototype a CXL-SSD on a custom FPGA platform and propose annotation mechanisms, Determinism and Bufferability, to enhance performance while preserving data persistency. Our simulation-based evaluation demonstrates that CXL-SSD achieves 10.9x better performance than PCIe-based memory expanders and further reduces latency by 5.4x with annotation enhancements. In workloads with high locality, CXL-SSD approaches DRAM-like performance due to efficient on-chip caching. This work highlights the feasibility of integrating block storage into CXL's ecosystem and provides a foundation for future memory-storage convergence.

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Miryeong Kwon, Donghyun Gouk, Junhyeok Jang, Jinwoo Baek, Hyunwoo You, Sangyoon Ji, Hongjoo Jung, Junseok Moon, Seungkwan Kang, Seungjun Lee, Myoungsoo Jung. 2025-06-18. From Block to Byte: Transforming PCIe SSDs with CXL Memory Protocol and Instruction Annotation. https://arxiv.org/abs/2506.15613

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