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arXiv · 2507.10561

SFATTI: Spiking FPGA Accelerator for Temporal Task-driven Inference -- A Case Study on MNIST

Alessio Caviglia·Filippo Marostica·Alessio Carpegna·Alessandro Savino·Stefano Di Carlo
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Abstract

Hardware accelerators are essential for achieving low-latency, energy-efficient inference in edge applications like image recognition. Spiking Neural Networks (SNNs) are particularly promising due to their event-driven and temporally sparse nature, making them well-suited for low-power Field Programmable Gate Array (FPGA)-based deployment. This paper explores using the open-source Spiker+ framework to generate optimized SNNs accelerators for handwritten digit recognition on the MNIST dataset. Spiker+ enables high-level specification of network topologies, neuron models, and quantization, automatically generating deployable HDL. We evaluate multiple configurations and analyze trade-offs relevant to edge computing constraints.

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Alessio Caviglia, Filippo Marostica, Alessio Carpegna, Alessandro Savino, Stefano Di Carlo. 2025-07-04. SFATTI: Spiking FPGA Accelerator for Temporal Task-driven Inference -- A Case Study on MNIST. https://doi.org/10.1109/icipw68931.2025.11385983

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