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arXiv · 2507.14139

SpeedLLM: An FPGA Co-design of Large Language Model Inference Accelerator

Peipei Wang·Wu Guan·Liping Liang·Zhijun Wang·Hanqing Luo·Zhibin Zhang
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Abstract

This paper introduces SpeedLLM, a neural network accelerator designed on the Xilinx Alevo U280 platform and optimized for the Tinyllama framework to enhance edge computing performance. Key innovations include data stream parallelism, a memory reuse strategy, and Llama2 operator fusion, which collectively reduce latency and energy consumption. SpeedLLM's data pipeline architecture optimizes the read-compute-write cycle, while the memory strategy minimizes FPGA resource demands. The operator fusion boosts computational density and throughput. Results show SpeedLLM outperforms traditional Tinyllama implementations, achieving up to 4.8* faster performance and 1.18* lower energy consumption, offering improvements in edge devices.

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Peipei Wang, Wu Guan, Liping Liang, Zhijun Wang, Hanqing Luo, Zhibin Zhang. 2025-05-07. SpeedLLM: An FPGA Co-design of Large Language Model Inference Accelerator. https://arxiv.org/abs/2507.14139

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