ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring

Dimitris Tsaras; Xing Li; Lei Chen; Zhiyao Xie; Mingxuan Yuan

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arXiv · 2508.08073

ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring

Dimitris Tsaras·Xing Li·Lei Chen·Zhiyao Xie·Mingxuan Yuan

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Abstract

In electronic design automation, logic optimization operators play a crucial role in minimizing the gate count of logic circuits. However, their computation demands are high. Operators such as refactor conventionally form iterative cuts for each node, striving for a more compact representation - a task which often fails 98% on average. Prior research has sought to mitigate computational cost through parallelization. In contrast, our approach leverages a classifier to prune unsuccessful cuts preemptively, thus eliminating unnecessary resynthesis operations. Experiments on the refactor operator using the EPFL benchmark suite and 10 large industrial designs demonstrate that this technique can speedup logic optimization by 3.9x on average compared with the state-of-the-art ABC implementation.

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Dimitris Tsaras, Xing Li, Lei Chen, Zhiyao Xie, Mingxuan Yuan. 2025-08-11. ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring. https://arxiv.org/abs/2508.08073

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