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arXiv · 2510.17831

Impact of Switching Layer Architecture on Power Consumption in RRAM

John F. Hardy II·Jack A. Garrard·Guilherme S. Y. Giardini·Carlo R. daCunha
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Abstract

This work demonstrates that porous helical WOx architectures enable a distinct low-power regime for planar ITO/WOx/ITO resistive random-access devices. While thin film and helical devices behave similarly at a 5 mA compliance, only helical devices sustain reproducible operation at 500 uA, where RESET voltages reduce by ~60%, switching currents decrease by 68-75%, and SET/RESET power drops by ~89% and ~83%. With helical devices operating at 500 uA, the memory window expands 400-600% due to selective suppression of high-resistive-state leakage, yielding both lower-power and improved read margin in a regime inaccessible to thin film devices. These results highlight geometry-driven field enhancement and confinement as practical design principles for low-power, high-margin resistive memories and point toward opportunities in transparent, flexible, and high-surface-area material systems.

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John F. Hardy II, Jack A. Garrard, Guilherme S. Y. Giardini, Carlo R. daCunha. 2025-10-02. Impact of Switching Layer Architecture on Power Consumption in RRAM. https://arxiv.org/abs/2510.17831

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