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arXiv · 2511.09527

Event-Driven Digital-Time-Domain Inference Architectures for Tsetlin Machines

Tian Lan·Rishad Shafik·Alex Yakovlev
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Abstract

Machine learning fits model parameters to approximate input-output mappings, predicting unknown samples. However, these models often require extensive arithmetic computations during inference, increasing latency and power consumption. This paper proposes a digital-time-domain computing approach for Tsetlin machine (TM) inference process to address these challenges. This approach leverages a delay accumulation mechanism to mitigate the costly arithmetic sums of classes and employs a Winner-Takes-All scheme to replace conventional magnitude comparators. Specifically, a Hamming distance-driven time-domain scheme is implemented for multi-class TMs. Furthermore, differential delay paths, combined with a leading-ones-detector logarithmic delay compression digital-time-domain scheme, are utilised for the coalesced TMs, accommodating both binary-signed and exponential-scale delay accumulation issues. Compared to the functionally equivalent, post-implementation digital TM architecture baseline, the proposed architecture demonstrates orders-of-magnitude improvements in energy efficiency and throughput.

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Tian Lan, Rishad Shafik, Alex Yakovlev. 2025-11-12. Event-Driven Digital-Time-Domain Inference Architectures for Tsetlin Machines. https://arxiv.org/abs/2511.09527

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