A 40 GHz Low-Power Variable-Gain Low Noise Amplifier in 28-nm CMOS Process

Harshith Reddy; Pankaj Arora

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arXiv · 2512.00443

A 40 GHz Low-Power Variable-Gain Low Noise Amplifier in 28-nm CMOS Process

Harshith Reddy·Pankaj Arora

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Abstract

A Low-Power Variable Gain (VG) mm-Wave Low Noise Amplifier (LNA) is designed and simulated in a 28-nm CMOS process. The LNA utilizes a simple, yet novel, technique presented in this paper to vary the small-signal output resistance to provide gain control. The amplifier also utilizes forward body biasing to reduce the supply voltage to 0.7 V and enhance power efficiency. A simultaneous noise and input matching (SNIM) technique is used to provide robust input matching and noise performance during gain adjustment. The proposed VG-LNA achieves a peak gain of 21 dB at 40.5 GHz with a noise figure of 2.8 dB and consumes only 4.5 mW. At the highest gain configuration, an input-referred 1-dB compression of -21 dBm and IP3 of -7.8 dBm are achieved, which increase to -14.8 dBm and 1.2 dBm, respectively, at the lowest gain configuration. Regardless of the gain control voltage, the LNA attains a very good FoM as compared to the state-of-the-art.

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BibTeX RIS

Harshith Reddy, Pankaj Arora. 2025-11-29. A 40 GHz Low-Power Variable-Gain Low Noise Amplifier in 28-nm CMOS Process. https://arxiv.org/abs/2512.00443

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