Timing-Error Optimized Architecture for Current-Steering DACs

Ramin Babaee; Shahab Oveis Gharan; Martin Bouchard

doi:10.1109/mwscas53549.2025.11244386

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arXiv · 2512.08903

Timing-Error Optimized Architecture for Current-Steering DACs

Ramin Babaee·Shahab Oveis Gharan·Martin Bouchard

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Abstract

We propose a novel digital-to-analog converter (DAC) weighting architecture that statistically minimizes the distortion caused by random timing mismatches among current sources. To decode the DAC input codewords into corresponding DAC switches, we present three algorithms with varying computational complexities. We perform high-level Matlab simulations to illustrate the dynamic performance improvement over the segmented structure.

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Ramin Babaee, Shahab Oveis Gharan, Martin Bouchard. 2025-12-09. Timing-Error Optimized Architecture for Current-Steering DACs. https://doi.org/10.1109/mwscas53549.2025.11244386

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