Hardware-Algorithm Co-Design for Hyperdimensional Computing Based on Memristive System-on-Chip

Yi Huang; Alireza Jaberi Rad; Qiangfei Xia

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arXiv · 2512.20808

Hardware-Algorithm Co-Design for Hyperdimensional Computing Based on Memristive System-on-Chip

Yi Huang·Alireza Jaberi Rad·Qiangfei Xia

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Abstract

Hyperdimensional computing (HDC), utilizing a parallel computing paradigm and efficient learning algorithm, is well-suited for resource-constrained artificial intelligence (AI) applications, such as in edge devices. In-memory computing (IMC) systems based on memristive devices complement this by offering energy-efficient hardware solutions. To harness the advantages of both memristive IMC hardware and HDC algorithms, we propose a hardware-algorithm co-design approach for implementing HDC on a memristive System-on-Chip (SoC). On the hardware side, we utilize the inherent randomness of memristive crossbar arrays for encoding and employ analog IMC for classification. At the algorithm level, we develop hardware-aware encoding techniques that map data features into hyperdimensional vectors, optimizing the classification process within the memristive SoC. Experimental results in hardware demonstrate 90.71% accuracy in the language classification task, highlighting the potential of our approach for achieving energy-efficient AI deployments on edge devices.

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Yi Huang, Alireza Jaberi Rad, Qiangfei Xia. 2025-12-23. Hardware-Algorithm Co-Design for Hyperdimensional Computing Based on Memristive System-on-Chip. https://arxiv.org/abs/2512.20808

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