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arXiv · 2512.21362

Power Side-Channel Analysis of the CVA6 RISC-V Core at the RTL Level Using VeriSide

Behnam Farnaghinejad·Antonio Porsia·Annachiara Ruospo·Alessandro Savino·Stefano Di Carlo·Ernesto Sanchez
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Abstract

Security in modern RISC-V processors demands more than functional correctness: It requires resilience to side-channel attacks. This paper evaluates the vulnerability of the side channel of the CVA6 RISC-V core by analyzing software-based AES encryption uses an RTL-level power profiling framework called VeriSide. This work represents that this design's Correlation Power Analysis (CPA) reveals significant leakage, enabling key recovery. These findings underscore the importance of early-stage RTL assessments in shaping future secure RISC-V designs.

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Behnam Farnaghinejad, Antonio Porsia, Annachiara Ruospo, Alessandro Savino, Stefano Di Carlo, Ernesto Sanchez. 2025-12-23. Power Side-Channel Analysis of the CVA6 RISC-V Core at the RTL Level Using VeriSide. https://arxiv.org/abs/2512.21362

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