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arXiv · 2603.29483

CXLRAMSim v1.0: System-Level Exploration of CXL Memory Expander Cards

Karan Pathak·David Atienza·Marina Zapater
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Abstract

The growing demands in the training and inference of Large Language Models (LLMs) are accelerating the adoption of scale-up systems that extend server shared memory through the use of Compute Express Link (CXL)-based load/store interconnects. Accurate full-system simulation of such architectures remains challenging, as existing tools (all very recent) rely on simplified or non-compliant architectural models, impacting accuracy and usability. We present CXLRAMSim, the first gem5-integrated, full-system simulator that models CXL devices at their correct position on the I/O bus, enabling the use of unmodified Linux kernels and software stack, realistic latency-bandwidth behavior and true interleaving with system DRAM. Our approach provides high-fidelity CXL.mem characterization and captures key challenges such as cache pollution when accessing CXL memory.

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Karan Pathak, David Atienza, Marina Zapater. 2026-03-31. CXLRAMSim v1.0: System-Level Exploration of CXL Memory Expander Cards. https://arxiv.org/abs/2603.29483

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