CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations

Yonghao Wang; Yang Yin; Hongqin Lyu; Jiaxin Zhou; Zhiteng Chao; Mingyu Shi; Wenchao Ding; Yunlin Du; Jing Ye; Tiancheng Wang; Huawei Li

arXiv · 2604.06607

CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations

Yonghao Wang·Yang Yin·Hongqin Lyu·Jiaxin Zhou·Zhiteng Chao·Mingyu Shi·Wenchao Ding·Yunlin Du·Jing Ye·Tiancheng Wang·Huawei Li

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Abstract

LLMs can generate SystemVerilog assertions (SVAs) from natural language specs, but single-pass outputs often lack functional coverage due to limited IC design understanding. We propose CoverAssert, an iterative framework that clusters semantic and AST-based structural features of assertions, maps them to specifications, and uses functional coverage feedback to guide LLMs in prioritizing uncovered points. Experiments on four open-source designs show that integrating CoverAssert with AssertLLM and Spec2Assertion improves average improvements of 9.57 % in branch coverage, 9.64 % in statement coverage, and 15.69 % in toggle coverage.

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BibTeX RIS

Yonghao Wang, Yang Yin, Hongqin Lyu, Jiaxin Zhou, Zhiteng Chao, Mingyu Shi, Wenchao Ding, Yunlin Du, Jing Ye, Tiancheng Wang, Huawei Li. 2026-04-08. CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations. https://arxiv.org/abs/2604.06607

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