Tunneling-Augmented Simulated Annealing for Short-Block LDPC Code Construction

Atharv Kanchi

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arXiv · 2604.07365

Tunneling-Augmented Simulated Annealing for Short-Block LDPC Code Construction

Atharv Kanchi

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Abstract

Designing high-performance error-correcting codes at short blocklengths is critical for low-latency communication systems, where decoding is governed by finite-length and graph-structural effects rather than asymptotic properties. This paper presents a global discrete optimization framework for constructing short-block linear codes by directly optimizing parity-check matrices. Code design is formulated as a constrained binary optimization problem with penalties for short cycles, trapping-set-correlated substructures, and degree violations. We employ a hybrid strategy combining tunneling-augmented simulated annealing (TASA) with classical local refinement to explore the resulting non-convex space. Experiments at blocklengths 64-128 over the AWGN channel show 0.1-1.3 dB SNR gains over random LDPC codes (average 0.45 dB) and performance within 0.6 dB of Progressive Edge Growth. In constrained regimes, the method enables design tradeoffs unavailable to greedy approaches. However, structural improvements do not always yield decoding gains: eliminating 1906 trapping set patterns yields only +0.08 dB improvement. These results position annealing-based global optimization as a complementary tool for application-specific code design under multi-objective constraints.

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Atharv Kanchi. 2026-04-01. Tunneling-Augmented Simulated Annealing for Short-Block LDPC Code Construction. https://arxiv.org/abs/2604.07365

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