Valley-Landscape Engineering in Bilayer WSe$_2$ Gate-All-Around Transistors

Abstract

The K-$\Gamma$ valence-band splitting $\Delta_{K\Gamma}$ that governs hole transport in few-layer WSe$_2$ is not a fixed material constant. It is tuned by interlayer stacking, strain, pressure, and the dielectric and displacement-field environment. Its computed value also depends on the level of electronic-structure theory. Bilayer WSe$_2$ therefore realizes a tunable multivalley landscape rather than a single operating point. We combine first-principles inputs with an analytical two-valley device model for gate-all-around (GAA) field-effect transistors, and obtain three results. (i) The minimum subthreshold swing stays near the thermionic limit of $60$~mV~dec$^{-1}$ independently of layer number, because well below threshold the quantum capacitance remains far below the oxide capacitance. (ii) The effective mobility is set by the K-to-$\Gamma$ occupation ratio: valley redistribution is strong when $\Delta_{K\Gamma}$ is of order $k_BT$ and fades toward single-valley $K$ transport as the splitting grows. (iii) In this small-splitting regime, biaxial strain tunes the effective mobility - and hence the on-current - through the valley population while the subthreshold swing stays at the thermionic limit, decoupling mobility control from electrostatic switching in a way distinct from scattering-based strategies. A symmetric GAA gate controls carrier density at essentially fixed splitting, and because an out-of-plane field increases $\Delta_{K\Gamma}$, its midplane-symmetric potential avoids driving the channel out of the small-splitting regime. The design principle has two facets: small $\Delta_{K\Gamma}$ - set by layer number, stacking, strain, and dielectric engineering - maximizes the valley tunability of $\mu_\mathrm{eff}$, whereas larger $\Delta_{K\Gamma}$, for example through compressive strain, suppresses the heavy $\Gamma$ valley and maximizes the on-state mobility.