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arXiv · 2606.14771

From MWM to iSLIP: A Linear-Algebraic Tutorial on Input-Queued Switch Scheduling

Abstract

This paper uses three objects -- the queue matrix Q, the matching matrix P, and the Lyapunov energy function V = ||Q||^2 -- as a shared mathematical language to explain, within a single framework, the scheduling objective of maximum weight matching (MWM), queue stability under admissible traffic (per-port loads strictly below 1), and the mechanics of iSLIP's Grant-Accept row-column decoupling together with the long-run average service matrix P-bar. The setting throughout is an N-by-N SoC crossbar, where each clock cycle permits at most one cell transfer per input-output port pair. For the experimental comparison, we built a C++ discrete-event simulator and used exact MWM (solved by the Hungarian algorithm) as the performance reference. All three approximate algorithms are given a fixed iteration budget: r = 3 rounds per cycle for iSLIP and for spectral scheduling, and r_sink = 10 Sinkhorn normalization rounds for entropy-regularized optimal transport (OT). Throughput and average cell delay are measured across four traffic patterns. Spectral scheduling and entropy-regularized OT track MWM closely in both throughput and delay across most tested conditions. iSLIP, by contrast, hits a throughput ceiling of roughly 80% under non-uniform admissible traffic at high load (unbalanced pattern w = 0.5, rho_load >= 0.9), with bottleneck queues growing without bound and delays reaching two orders of magnitude above MWM. Under uniform traffic this breakdown does not occur: at rho_load = 0.99 iSLIP delay is about 3.7x that of MWM. The performance gains of spectral scheduling and OT come at an additional per-cycle compute cost on the order of O(r*N^2) multiply-accumulate or exponential operations; whether this overhead is feasible in real hardware -- in terms of die area, power, and timing closure -- remains to be evaluated.

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BibTeXRIS

Xiaotong Yuan, An Guo. 2026-06-09. From MWM to iSLIP: A Linear-Algebraic Tutorial on Input-Queued Switch Scheduling. https://arxiv.org/abs/2606.14771

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