Ion-Implanted Silicon Nanoregions Enable Ultra-Low-Loss Trimming of Cladded Photonic Integrated Circuits

Abstract

Photonic integrated circuits (PICs) have emerged as a key platform for information processing, including optical communication and computing. As PIC complexity increases, fabrication-induced response deviations accumulate, making post-fabrication trimming critical for unlocking their full potential. Here, we demonstrate that silicon ion implantation enables scalable, ultra-low-loss trimming of cladded PICs by locally forming a high-index silicon-rich region. Structural characterization confirms that the silicon-implanted nanoregion is confined to the cladding without observable damage to the underlying waveguide. The implantation-induced excess loss is below 0.001 dB per {\pi} phase shift, while the optical response remains stable over a four-month observation period. Automated trimming is demonstrated on a photonic crossbar array, reducing the average channel output variation from 78.5% to 5.9%. These results establish a practical route towards automated, ultra-low-loss post-fabrication trimming for large-scale cladded PICs.