Bridging AQFP Technology Legalization and Physical Design: Layout-Aware Buffer and Splitter Insertion via Width--Depth Product Minimization

Abstract

Adiabatic Quantum Flux Parametron (AQFP) is an emerging superconducting technology that enables ultra-low energy dissipation approaching the Shannon limit. However, its gate-level pipelining and explicit fanout constraints require technology legalization through buffer and splitter insertion to ensure path balancing and signal distribution, becoming a critical and costly step in the design flow. Prior work has focused on minimizing inserted cell count and logic depth, yet these objectives do not accurately capture the final physical design cost, which is fundamentally governed by the product of circuit width and depth. In this article, we redefine AQFP buffer and splitter insertion optimization as minimizing the circuit width--depth product, a layout-aware metric that more accurately captures physical design area than prior cell minimization efforts. We are the first to formulate buffer and splitter insertion under this objective and prove that the resulting problem is NP-complete. To address this complexity, we develop scalable heuristics that integrates legalization with this objective. Experimental results on standard benchmarks demonstrate that our approach achieves an average 30% reduction in post-placement area compared to state-of-the-art methods, with only a 3% increase in junction count, and on individual circuits up to 61% area reduction, demonstrating the effectiveness of the proposed objective in reducing true design cost.