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arXiv · 2608.18156

FPGA Lifecycle Management for RISC-V Systems

Tianhai Liu·James J. Hunt
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Abstract

FPGA lifecycle management remains tied to proprietary toolchains and host architectures, leaving RISC-V without a vendor-neutral model for scalable bitstream deployment. A host-agnostic control-plane architecture is presented that shifts lifecycle management to the operating-system layer by leveraging standard Linux capabilities, thereby decoupling deployment from specific ISAs and vendor stacks. This enables Linux-capable RISC-V processors to serve as control hosts in heterogeneous FPGA systems. Prototyped on a Zynq-7000 SoC and generalizable to RISC-V platforms, the architecture provides a portable foundation for fleet-scale FPGA management.

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Tianhai Liu, James J. Hunt. 2026-08-13. FPGA Lifecycle Management for RISC-V Systems. https://doi.org/10.5445/ir%2F1000193590

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