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arXiv · 2608.22202

Lessons from the Hardware Hacking Competitions: Verification Techniques, Findings, and Insights

Sudipta Paria·Aritra Dasgupta·Raghul Saravanan·Jayanth Thangellamudi·Sai Manoj P D·Swarup Bhunia
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Abstract

Hardware hacking competitions have emerged as practical platforms for evaluating security weaknesses in complex System-on-Chip (SoC) designs while promoting security-aware verification and tool development. This paper presents a systematic study of SoC security verification through open-box hardware hacking competitions, focusing on practical vulnerability analysis strategies, observed findings, and lessons for security-aware verification. We present a multi-strategy vulnerability analysis methodology, combining simulation-based verification, formal verification, lint analysis, Large Language Model (LLM)-assisted bug detection, and coverage-guided hybrid fuzzing. Representative vulnerability findings are analyzed to illustrate how different techniques expose complementary classes of security flaws, and we derive practical lessons for pre-silicon security verification. Finally, we discuss how competition benchmarks can support the reproducible evaluation of emerging hardware security techniques and guide future security-aware EDA research.

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Sudipta Paria, Aritra Dasgupta, Raghul Saravanan, Jayanth Thangellamudi, Sai Manoj P D, Swarup Bhunia. 2026-08-23. Lessons from the Hardware Hacking Competitions: Verification Techniques, Findings, and Insights. https://arxiv.org/abs/2608.22202

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