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arXiv · 2610.06058

Efficient HQC Implementations on RISC-V: A Cross-Layer Design Space Exploration

Maximilian Schöffel·Johannes Feldmann·Elias Biehl·Norbert Wehn
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Abstract

RISC-V-based hardware/software co-design has become an established methodology for implementing post-quantum cryptography (PQC) on embedded devices. Its software programmability, extensible instruction-set architecture, and optional dedicated accelerators create a broad design space that offers the flexibility required for crypto-agility and post-deployment updates. For HQC, a PQC key-encapsulation mechanism selected for standardization, several RISC-V-based implementations have already been published. However, these works explore only a small subset of this design space. We present, to the best of our knowledge, the most comprehensive exploration of RISC-V-based HQC. Our exploration is centered around a new, parametrizable architecture framework on which we characterize 29,920 distinct architectural configurations across all three HQC security levels on FPGA. The Pareto-optimal configurations from this framework outperform the state-of-the-art RISC-V-based HQC implementation, ranging from 4.8x lower LUT utilization at 17% lower latency to 69.6x lower latency at 30% lower LUT utilization, while also requiring up to 10.6x fewer block RAMs.

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Maximilian Schöffel, Johannes Feldmann, Elias Biehl, Norbert Wehn. 2026-10-05. Efficient HQC Implementations on RISC-V: A Cross-Layer Design Space Exploration. https://arxiv.org/abs/2610.06058

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