ML-Assisted Power Side-Channel Attacks on ML Accelerators in Shared FPGAs

Abstract

Cloud providers offer on-demand access to Field-Programmable Gate Arrays (FPGAs), and multi-tenant FPGAs let multiple users share one device to improve utilization. This sharing introduces security risks: an adversary co-located with a victim on the same FPGA can mount power side-channel attacks against the victim's Machine Learning (ML) accelerator. Prior on-chip attacks on such accelerators based on Time-to-Digital Converter (TDC) sensors have recovered only small, MNIST-scale grayscale inputs, including with ML-assisted reconstruction. This work is the first on-chip, TDC-based attack to produce full-scale color reconstructions of ImageNet-scale inputs, by combining ML-based upscaling and recoloring with TDC measurements of a remote victim's ML accelerator. We frame this as a proof-of-concept leakage study: the victim implements the first convolution layer of a CNN processing 224x224 ImageNet inputs on a shared FPGA, which we isolate to characterize the input-dependent leakage, and we quantify how much of each reconstruction reflects genuinely recovered information versus ML-generated post-processing. As a preliminary countermeasure, we study a pixel-substitution defense that replaces each pixel value, within a fixed intensity budget, with one of different Hamming Weight, producing a different TDC signature. We find that this transformation costs the victim's own model more accuracy than it costs the attacker and, because it applies the same fixed, publicly reconstructable mapping to every image, is largely defeated by an attacker retrained on the transformed data; robust defenses will require randomized or input-dependent transformations.