Decoupling Trap States in Amorphous Oxide Semiconductor Transistor Using a Conductive-Semiconducting-Conductive MOS Structure

Abstract

We propose a novel amorphous oxide semiconductor (AOS)-based conductive-semiconducting-conductive (CSC) MOS test structure to effectively sense, discriminate, and analyze distinct trap-induced conductance losses in AOS transistors. In conventional test structures, non-ideal metal-AOS contacts convolute the conductance loss generated by various trap states. The CSC architecture mitigates these contact-related artifacts, enabling the decoupling of interface states and shallow states. Furthermore, the contributions from leakage, series resistance, and device-geometry effects are identified and calibrated. Our results yield bias-resolved trap profiles and reveal three distinct regimes: (1) In the depletion region, interface states dominate the conductance loss. These states exhibit sub-microsecond time constants and their density increases slightly with deeper depletion, which is associated with donor-like states. (2) From weak to moderate accumulation, shallow states become the primary contributor, displaying a Gaussian-like volumetric density-of-states distribution with response times spanning from microseconds to nanoseconds. (3) In the strong accumulation regime, interface states regain dominance with an increased state quantity, while their time constants remain invariant. These bias-resolved profiles clarify how different trap populations impact AOS transistors under distinct operating conditions, providing intuitive metrics for understanding reliability degradation. Consequently, the CSC structure offers a simple, scalable, and robust platform for trap characterization in AOS transistors.