Hierarchical Signal Temporal Logic Control of Continuous-Time Systems

Abstract

For linear continuous-time systems, we solve the signal temporal logic (STL) control problem by translating it from continuous to discrete time such that a solution to the discrete-time problem guarantees a solution to the original continuous-time one. We split control synthesis into three hierarchical tasks. First, we discretize the continuous-time STL formula into a discrete-time one by sampling the temporal behavior it specifies. We accordingly discretize the continuous-time system by constructing a discrete-time model such that the input-state trajectories of the continuous-time system can be characterized as piecewise polynomial interpolations of the input-state trajectories of the discrete-time model. Second, we exploit this characterization to formulate mixed-integer linear constraints on the discrete-time trajectories that allow for planning a trajectory whose piecewise polynomial interpolation satisfies the continuous-time STL formula. In fact, system discretization and trajectory planning are performed in such a manner that any feasible solution to these constraints gives a discrete-time trajectory that can be transformed into a continuous-time one guaranteed to satisfy the original STL formula. Third, we propose a step-by-step algorithm to construct the control input that realizes such continuous-time trajectory.