arXiv subjects

A. M. J. Zwerver

Publications and source records attributed to A. M. J. Zwerver.

6 recordsLinked to original sources

arXiv2026

Simultaneous operation of an 18-qubit modular array in germanium

Utility-scale quantum computing requires the integration and operation of a large-scale qubit register. Semiconductor spin qubits are a primary candidate for this, due to the prospects of building integrated hybrid quantum-classical architectures. However, scaling spin-qubit systems while preserving performance and control has remained a challenge. Here, we demonstrate the operation of an 18-qubit array in germanium based on an extendable 2xN architecture. We achieve simultaneous initialization, control, and readout across the entire array, enabled by parallel operation of modular unit cells. Across the array, we achieve average and median single-qubit gate fidelities of 99.8% and 99.9%, respectively. Finally, we characterize the nearest-neighbor exchange couplings throughout the device and implement high-quality controlled-Z gates to generate a three-qubit Greenberger-Horne-Zeilinger (GHZ) state. These results demonstrate that spin-qubit arrays can be scaled while maintaining high-fidelity operation and establish a modular, extendable architecture for planar semiconductor quantum processors.

cond-mat.mes-hall↗

arXiv2022

Reducing charge noise in quantum dots by using thin silicon quantum wells

Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a $^{28}$Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick $^{28}$Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29$\pm$0.02 $μ$eV/sqrt(Hz) at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to cz-gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system.

cond-mat.mes-hall↗

arXiv2022

Shuttling an electron spin through a silicon quantum dot array

Coherent links between qubits separated by tens of micrometers are expected to facilitate scalable quantum computing architectures for spin qubits in electrically-defined quantum dots. These links create space for classical on-chip control electronics between qubit arrays, which can help to alleviate the so-called wiring bottleneck. A promising method of achieving coherent links between distant spin qubits consists of shuttling the spin through an array of quantum dots. Here, we use a linear array of four tunnel-coupled quantum dots in a 28Si/SiGe heterostructure to create a short quantum link. We move an electron spin through the quantum dot array by adjusting the electrochemical potential for each quantum dot sequentially. By pulsing the gates repeatedly, we shuttle an electron forward and backward through the array up to 250 times, which corresponds to a total distance of approximately 80 μm. We make an estimate of the spin-flip probability per hop in these experiments and conclude that this is well below 0.01% per hop.

cond-mat.mes-hall↗

arXiv2021

Qubits made by advanced semiconductor manufacturing

Full-scale quantum computers require the integration of millions of quantum bits. The promise of leveraging industrial semiconductor manufacturing to meet this requirement has fueled the pursuit of quantum computing in silicon quantum dots. However, to date, their fabrication has relied on electron-beam lithography and, with few exceptions, on academic style lift-off processes. Although these fabrication techniques offer process flexibility, they suffer from low yield and poor uniformity. An important question is whether the processing conditions developed in the manufacturing fab environment to enable high yield, throughput, and uniformity of transistors are suitable for quantum dot arrays and do not compromise the delicate qubit properties. Here, we demonstrate quantum dots hosted at a 28Si/28SiO2 interface, fabricated in a 300 mm semiconductor manufacturing facility using all-optical lithography and fully industrial processing. As a result, we achieve nanoscale gate patterns with remarkable homogeneity. The quantum dots are well-behaved in the multi-electron regime, with excellent tunnel barrier control, a crucial feature for fault-tolerant two-qubit gates. Single-spin qubit operation using magnetic resonance reveals relaxation times of over 1 s at 1 Tesla and coherence times of over 3 ms, matching the quality of silicon spin qubits reported to date. The feasibility of high-quality qubits made with fully-industrial techniques strongly enhances the prospects of a large-scale quantum computer

cond-mat.mes-hall↗

arXiv2020

On-chip Integration of Si/SiGe-based Quantum Dots and Switched-capacitor Circuits

Solid-state qubits integrated on semiconductor substrates currently require at least one wire from every qubit to the control electronics, leading to a so-called wiring bottleneck for scaling. Demultiplexing via on-chip circuitry offers an effective strategy to overcome this bottleneck. In the case of gate-defined quantum dot arrays, specific static voltages need to be applied to many gates simultaneously to realize electron confinement. When a charge-locking structure is placed between the quantum device and the demultiplexer, the voltage can be maintained locally. In this study, we implement a switched-capacitor circuit for charge-locking and use it to float the plunger gate of a single quantum dot. Parallel plate capacitors, transistors and quantum dot devices are monolithically fabricated on a Si/SiGe-based substrate to avoid complex off-chip routing. We experimentally study the effects of the capacitor and transistor size on the voltage accuracy of the floating node. Furthermore, we demonstrate that the electrochemical potential of the quantum dot can follow a 100 Hz pulse signal while the dot is partially floating, which is essential for applying this strategy in qubit experiments.

cond-mat.mes-hall↗

arXiv2019

Loading a quantum-dot based "Qubyte" register

Electrostatically defined quantum dot arrays offer a compelling platform for quantum computation and simulation. However, tuning up such arrays with existing techniques becomes impractical when going beyond a handful of quantum dots. Here, we present a method for systematically adding quantum dots to an array one dot at a time, in such a way that the number of electrons on previously formed dots is unaffected. The method allows individual control of the number of electrons on each of the dots, as well as of the interdot tunnel rates. We use this technique to tune up a linear array of eight GaAs quantum dots such that they are occupied by one electron each. This new method overcomes a critical bottleneck in scaling up quantum-dot based qubit registers.

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