arXiv subjects

A. Valero

Publications and source records attributed to A. Valero.

6 recordsLinked to original sources

arXiv2026

FPGA Acceleration of Matrix-Element Calculations for Monte Carlo Event Generation

We present an FPGA-based study of matrix-element acceleration for Monte Carlo event generation, using MadGraph5_aMC@NLO as a benchmark framework. Two complementary scenarios are considered. First, we implement the full matrix-element workflow on an AMD Alveo U250 accelerator for the benchmark process $e^+e^- \to \mu^+\mu^-$, enabling an end-to-end evaluation of FPGA acceleration for a simple process. Second, for the more complex $gg \to t\bar{t}+X$ processes with increasing jet multiplicity, we investigate FPGA acceleration of the color-algebra kernels as a structured and scalable entry point for selective acceleration. In this second case, the reported speedups correspond to the isolated color-reduction kernel operating on precomputed amplitudes, rather than to the full matrix-element evaluation or the complete event-generation workflow. The proposed implementations are developed using High-Level Synthesis and are evaluated in terms of numerical accuracy, performance, energy efficiency, resource utilization, and scalability. Compared with CPU and GPU implementations available within the MG5aMC framework, the FPGA solutions achieve substantial speedups and significantly improved energy efficiency. For the considered benchmarks, the numerical results remain in close agreement with the corresponding CPU reference calculations, while the resource analysis highlights the importance of numerical representation in determining scalability on FPGA devices. These results support the use of FPGAs as a competitive architecture for selected Monte Carlo event-generation workloads in high-energy physics.

hep-ex↗

arXiv2026

Cascade Pipeline for Leading-Order Matrix Element Evaluation on AMD Versal AI Engine Arrays

A major computational bottleneck in modern High Energy Physics event generators arises from the integration of the matrix element, which requires repeated evaluations at different phase-space points to cover all possible initial- and final-state configurations. As the Large Hadron Collider enters its High-Luminosity phase, the demand for energy-efficient acceleration is expected to exceed the limits of conventional CPU scaling, motivating the use of highly parallel computing platforms such as graphics processing units (GPUs). In this work, we present an alternative approach based on a cascade pipeline architecture for evaluating leading-order matrix elements of the \ggttg process on AMD Versal AI Engine (\aie) arrays. Due to the 16\,kB per-tile program memory constraint, the computation is decomposed into a five-stage pipeline, with stages communicating via a wavefunction-token protocol over the on-chip cascade interface. Mapping 80 independent pipelines onto the 400 \aie tiles of the VCK190 platform yields a projected throughput of $1.0\times10^6$ matrix element evaluations per second at 54.8\,W, corresponding to a $34\times$ speedup over a single CPU core and a $7.7\times$ improvement in energy efficiency. Numerical agreement with the \amcnlo double-precision reference is validated at the parts-per-million level in mean relative error.

hep-ex↗

arXiv2024

Study of the Radiation Hardness of the ATLAS Tile Calorimeter Optical Instrumentation with Run 2 data

This paper presents a study of the radiation hardness of the hadronic Tile Calorimeter of the ATLAS experiment in the LHC Run 2. Both the plastic scintillators constituting the detector active media and the wavelength-shifting optical fibres collecting the scintillation light into the photodetector readout are elements susceptible to radiation damage. The dedicated calibration and monitoring systems of the detector (caesium radioactive sources, laser and minimum bias integrator) allow to assess the response of these optical components. Data collected with these systems between 2015 and 2018 are analysed to measure the degradation of the optical instrumentation across Run 2. Moreover, a simulation of the total ionising dose in the calorimeter is employed to study and model the degradation profile as a function of the exposure conditions, both integrated dose and dose rate. The measurement of the relative light output loss in Run 2 is presented and extrapolations to future scenarios are drawn based on current data. The impact of radiation damage on the cell response uniformity is also analysed.

physics.ins-det↗

arXiv2020

Operational experience and evolution of the ATLAS Tile Hadronic Calorimeter Read-Out Drivers

TileCal is the central hadronic calorimeter of the ATLAS experiment at the Large Hadron Collider (LHC). It is a sampling detector where scintillating tiles are embedded in steel absorber plates. The tiles are grouped forming cells, which are read-out on both sides by photomultiplier tubes (PMTs). The PMT digital samples are transmitted to the Read-Out Drivers (ROD) located in the back-end system for the events accepted by the Level 1 trigger system. The ROD is the core element of the back-end electronics and it represents the interface between the front-end electronics and the ATLAS overall Data AcQuisition (DAQ) system. It is responsible for energy and time reconstruction, trigger and data synchronization, busy handling, data integrity checking and lossless data compression. The TileCal ROD is a standard 9U VME board equipped with DSP based Processing Units mezzanine cards. A total of 32 ROD modules are required to read-out the entire TileCal detector. Each ROD module has to process the data from up to 360 PMTs in real time in less than 10 microseconds. The commissioning of the RODs was completed in 2008 before the first LHC collisions. Since then, several hardware and firmware updates have been implemented to accommodate the RODs to the evolving ATLAS Trigger and DAQ conditions adjusted to follow the LHC parameters. The initial ROD system, the different updates implemented and the operational experience during the LHC Run 1 and Run 2 are presented.

physics.ins-det↗

arXiv2019

FPGA implementation of a deep learning algorithm for real-time signal reconstruction in radiation detectors under high pile-up conditions

The analog signals generated in the read-out electronics of radiation detectors are shaped prior to the digitization in order to improve the signal to noise ratio (SNR). The real amplitude of the analog signal is then obtained using digital filters, which provides information about the energy deposited in the detector. The classical digital filters have a good performance in ideal situations with Gaussian electronic noise and no pulse shape distortion. However, high-energy particle colliders, such as the Large Hadron Collider (LHC) at CERN, can produce multiple simultaneous radiation events, which produce signal pileup. The performance of classical digital filters deteriorates in these conditions since the signal pulse shape gets distorted. In addition, this type of experiments produces a high rate of collisions, which requires high throughput data acquisitions systems. In order to cope with these harsh requirements, new read-out electronics systems are based on high-performance FPGAs, which permit the utilization of more advanced real-time signal reconstruction algorithms. In this paper, a deep learning method is proposed for real-time signal reconstruction in high pileup radiation detectors. The performance of the new method has been studied using simulated data and the results are compared with a classical FIR filter method. In particular, the signals and FIR filter used in the ATLAS Tile Calorimeter are used as benchmark. The implementation, resources usage and performance of the proposed Neural Network algorithm in FPGA are also presented.

physics.ins-det↗

arXiv2018

Clock Distribution and Readout Architecture for the ATLAS Tile Calorimeter at the HL-LHC

The Tile Calorimeter (TileCal) is one detector of the ATLAS experiment at the Large Hadron Collider (LHC). TileCal is a sampling calorimeter made of steel plates and plastic scintillators which are readout using approximately 10,000 PhotoMultipliers Tubes (PMTs). In 2024, the LHC will undergo a series of upgrades towards a High Luminosity LHC (HL-LHC) to deliver up to 7.5 times the current nominal instantaneous luminosity. The ATLAS Tile Phase II Upgrade will accommodate detector and Data AcQuisition (DAQ) system to the HL-LHC requirements. The detector electronics will be redesigned using a new clock distribution and readout architecture with a full-digital trigger system. After the Long Shutdown 3 (2024-2026), the on-detector electronics will transfer digitized data for every bunch crossing (~25 ns) to the Tile PreProcessors (TilePPr) in the counting rooms with a total data bandwidth of 40 Tbps. The TilePPrs will store the detector data in pipeline memories to cope with the new ATLAS DAQ architecture requirements, and will interface with the Front End Link eXchange (FELIX) system and the first trigger level. The TilePPr boards will distribute the sampling clock to the on-detector electronics for synchronization with the LHC clock using high-speed links configured for fixed and deterministic latency. The upgraded readout and clock distribution strategy was fully validated in a Demonstrator system using prototypes of the upgraded electronics in several test beam campaigns between 2015 and 2018.

physics.ins-det↗