Aakrati Jain | Searcharxiv

arXiv2026

A Multiscale Workflow for Thermal Analysis of 3DI Chip Stacks

Thermally aware design of 2.5D and 3D advanced packaging systems will require fast, accurate, and powerful thermal analysis of chiplets, stacks, and packages. These systems contain multiple materials with non-linear heat transfer properties and geometric feature sizes that span many orders of magnitude. The smallest heterostructures in the front and back ends of the line present significant thermal modeling and analysis challenges in isolation. Replicated millions or billions of times in a chiplet stack, these structures present a near insurmountable hurdle to meeting the speed and accuracy needed of analysis in the design process. Additionally, establishing precise parameter values for the materials in these systems, when size and temperature dependencies create significant deviations from bulk properties, further complicates the problem. To address these issues, we have developed a multiscale methodology that advances the current state of the field by enabling die-scale simulations that capture phenomena arising from the structural details of the BEOL metallization stack. Taking advantage of the large length-scale separation between the BEOL features and the die-level structures, we employ a hierarchical, multiscale, finite-element approach. This hierarchical method uses a standard finite element method (FEM) formulation on a die or package scale, using computational homogenization to obtain effective thermal conductivities in the BEOL. Referring to industry-standard layout and design files, we construct and solve a locally appropriate subscale FEM problem in a representative volume element (RVE) at every quadrature point in the macroscale FEM problem. To accomplish this, RVE models are automatically constructed, meshed, and used to compute homogenized, anisotropic, thermal conductivities from the relevant GDSII or OASIS.

cs.OH↗

arXiv2025

DiffChip: Thermally Aware Chip Placement with Automatic Differentiation

Chiplets are modular integrated circuits that can be combined to form a larger system, offering flexibility and performance enhancements. However, their dense packing often leads to significant thermal management challenges, requiring careful floorplanning to ensure efficient heat distribution. To address thermal considerations, layout optimization algorithms concurrently minimize the total wirelength and the maximum temperature. However, these efforts employ gradient-free approaches, such as simulated annealing, which suffer from poor scaling and slow convergence. In this paper, we propose DiffChip, a chiplet placement algorithm based on automatic differentiation (AD). The proposed framework relies on a differentiable thermal solver that computes the sensitivity of the temperature map with respect to the positions of the chiplets. Regularization strategies for peak temperature, heat sources, and material properties enable end-to-end differentiability, allowing for gradient-based optimization. We apply DiffChip to optimize a layout where the total wirelength is minimized while keeping the maximum temperature below a desired threshold. By leveraging AD and physics-aware optimization, our approach accelerates the design process of microelectronic systems, exceeding traditional trial-and-error and gradient-free methods.

physics.comp-ph↗