arXiv subjects

Abdel-Hameed A. Badawy

Publications and source records attributed to Abdel-Hameed A. Badawy.

30 records · Page 2Linked to original sources

arXiv2024

Trojan Playground: A Reinforcement Learning Framework for Hardware Trojan Insertion and Detection

Current Hardware Trojan (HT) detection techniques are mostly developed based on a limited set of HT benchmarks. Existing HT benchmark circuits are generated with multiple shortcomings, i.e., i) they are heavily biased by the designers' mindset when created, and ii) they are created through a one-dimensional lens, mainly the signal activity of nets. We introduce the first automated Reinforcement Learning (RL) HT insertion and detection framework to address these shortcomings. In the HT insertion phase, an RL agent explores the circuits and finds locations best for keeping inserted HTs hidden. On the defense side, we introduce a multi-criteria RL-based HT detector that generates test vectors to discover the existence of HTs. Using the proposed framework, one can explore the HT insertion and detection design spaces to break the limitations of human mindset and benchmark issues, ultimately leading toward the next generation of innovative detectors. We demonstrate the efficacy of our framework on ISCAS-85 benchmarks, provide the attack and detection success rates, and define a methodology for comparing our techniques.

cs.CR↗

arXiv2024

The Seeker's Dilemma: Realistic Formulation and Benchmarking for Hardware Trojan Detection

This work focuses on advancing security research in the hardware design space by formally defining the realistic problem of Hardware Trojan (HT) detection. The goal is to model HT detection more closely to the real world, i.e., describing the problem as "The Seeker's Dilemma" (an extension of Hide&Seek on a graph), where a detecting agent is unaware of whether circuits are infected by HTs or not. Using this theoretical problem formulation, we create a benchmark that consists of a mixture of HT-free and HT-infected restructured circuits while preserving their original functionalities. The restructured circuits are randomly infected by HTs, causing a situation where the defender is uncertain if a circuit is infected or not. We believe that our innovative dataset will help the community better judge the detection quality of different methods by comparing their success rates in circuit classification. We use our developed benchmark to evaluate three state-of-the-art HT detection tools to show baseline results for this approach. We use Principal Component Analysis to assess the strength of our benchmark, where we observe that some restructured HT-infected circuits are mapped closely to HT-free circuits, leading to significant label misclassification by detectors.

cs.CR↗

arXiv2023

LLVM Static Analysis for Program Characterization and Memory Reuse Profile Estimation

Profiling various application characteristics, including the number of different arithmetic operations performed, memory footprint, etc., dynamically is time- and space-consuming. On the other hand, static analysis methods, although fast, can be less accurate. This paper presents an LLVM-based probabilistic static analysis method that accurately predicts different program characteristics and estimates the reuse distance profile of a program by analyzing the LLVM IR file in constant time, regardless of program input size. We generate the basic-block-level control flow graph of the target application kernel and determine basic-block execution counts by solving the linear balance equation involving the adjacent basic blocks' transition probabilities. Finally, we represent the kernel memory accesses in a bracketed format and employ a recursive algorithm to calculate the reuse distance profile. The results show that our approach can predict application characteristics accurately compared to another LLVM-based dynamic code analysis tool, Byfl.

cs.SE↗

arXiv2023

Predicting Expressibility of Parameterized Quantum Circuits using Graph Neural Network

Parameterized Quantum Circuits (PQCs) are essential to quantum machine learning and optimization algorithms. The expressibility of PQCs, which measures their ability to represent a wide range of quantum states, is a critical factor influencing their efficacy in solving quantum problems. However, the existing technique for computing expressibility relies on statistically estimating it through classical simulations, which requires many samples. In this work, we propose a novel method based on Graph Neural Networks (GNNs) for predicting the expressibility of PQCs. By leveraging the graph-based representation of PQCs, our GNN-based model captures intricate relationships between circuit parameters and their resulting expressibility. We train the GNN model on a comprehensive dataset of PQCs annotated with their expressibility values. Experimental evaluation on a four thousand random PQC dataset and IBM Qiskit's hardware efficient ansatz sets demonstrates the superior performance of our approach, achieving a root mean square error (RMSE) of 0.03 and 0.06, respectively.

quant-ph↗

arXiv2023

Multi-criteria Hardware Trojan Detection: A Reinforcement Learning Approach

Hardware Trojans (HTs) are undesired design or manufacturing modifications that can severely alter the security and functionality of digital integrated circuits. HTs can be inserted according to various design criteria, e.g., nets switching activity, observability, controllability, etc. However, to our knowledge, most HT detection methods are only based on a single criterion, i.e., nets switching activity. This paper proposes a multi-criteria reinforcement learning (RL) HT detection tool that features a tunable reward function for different HT detection scenarios. The tool allows for exploring existing detection strategies and can adapt new detection scenarios with minimal effort. We also propose a generic methodology for comparing HT detection methods fairly. Our preliminary results show an average of 84.2% successful HT detection in ISCAS-85 benchmark

cs.AR↗

arXiv2022

Quantum Netlist Compiler (QNC)

Over the last decade, Quantum Computing hardware has rapidly developed and become a very intriguing, promising, and active research field among scientists worldwide. To achieve the desired quantum functionalities, quantum algorithms require translation from a high-level description to a machine-specific physical operation sequence. In contrast to classical compilers, state-of-the-art quantum compilers are in their infancy. We believe there is a research need for a quantum compiler that can deal with generic unitary operators and generate basic unitary operations according to quantum machines' diverse underlying technologies and characteristics. In this work, we introduce the Quantum Netlist Compiler (QNC) that converts arbitrary unitary operators or desired initial states of quantum algorithms to OpenQASM-2.0 circuits enabling them to run on actual quantum hardware. Extensive simulations were run on the IBM quantum systems. The results show that QNC is well suited for quantum circuit optimization and produces circuits with competitive success rates in practice.

quant-ph↗

arXiv2022

A Divide-and-Conquer Approach to Dicke State Preparation

We present a divide-and-conquer approach to deterministically prepare Dicke states $\lvert D_k^n\rangle$ (i.e., equal-weight superpositions of all $n$-qubit states with Hamming Weight $k$) on quantum computers. In an experimental evaluation for up to $n=6$ qubits on IBM Quantum Sydney and Montreal devices, we achieve significantly higher state fidelity compared to previous results [Mukherjee and others, TQE'2020], [Cruz and others, QuTe'2019]. The fidelity gains are achieved through several techniques: Our circuits first "divide" the Hamming weight between blocks of $n/2$ qubits, and then "conquer" those blocks with improved versions of Dicke state unitaries [Bärtschi and others, FCT'2019]. Due to the sparse connectivity on IBM's heavy-hex-architectures, these circuits are implemented for linear nearest neighbor topologies. Further gains in (estimating) the state fidelity are due to our use of measurement error mitigation and hardware progress.

quant-ph↗

arXiv2022

Hardware Trojan Insertion Using Reinforcement Learning

This paper utilizes Reinforcement Learning (RL) as a means to automate the Hardware Trojan (HT) insertion process to eliminate the inherent human biases that limit the development of robust HT detection methods. An RL agent explores the design space and finds circuit locations that are best for keeping inserted HTs hidden. To achieve this, a digital circuit is converted to an environment in which an RL agent inserts HTs such that the cumulative reward is maximized. Our toolset can insert combinational HTs into the ISCAS-85 benchmark suite with variations in HT size and triggering conditions. Experimental results show that the toolset achieves high input coverage rates (100\% in two benchmark circuits) that confirms its effectiveness. Also, the inserted HTs have shown a minimal footprint and rare activation probability.

cs.LG↗

arXiv2019

Modeling Shared Cache Performance of OpenMP Programs using Reuse Distance

Performance modeling of parallel applications on multicore computers remains a challenge in computational co-design due to the complex design of multicore processors including private and shared memory hierarchies. We present a Scalable Analytical Shared Memory Model to predict the performance of parallel applications that runs on a multicore computer and shares the same level of cache in the hierarchy. This model uses a computationally efficient, probabilistic method to predict the reuse distance profiles, where reuse distance is a hardware architecture-independent measure of the patterns of virtual memory accesses. It relies on a stochastic, static basic block-level analysis of reuse profiles measured from the memory traces of applications ran sequentially on small instances rather than using a multi-threaded trace. The results indicate that the hit-rate predictions on the shared cache are accurate.

cs.PF↗

arXiv2018

Energy Efficient Tri-State CNFET Ternary Logic Gates

Traditional silicon binary circuits continue to face challenges such as high leakage power dissipation and large area of interconnections. Multiple-Valued Logic (MVL) and nano devices are two feasible solutions to overcome these problems. In this paper, a novel method is presented to design ternary logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs). The proposed designs use the unique properties of CNFETs, for example, adjusting the Carbon Nanontube (CNT) diameters to have the desired threshold voltage and have the same mobility of P-FET and N-FET transistors. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state which saves power while the circuits are not in use. In an effort to show a more detailed application of our approach, we design a 2-digit adder-subtractor circuit. We simulate the proposed ternary circuits using HSPICE via standard 32nm CNFET technology. The simulation results indicate the correct operation of the designs under different process, voltage and temperature (PVT) variations. Moreover, a power efficient ternary logic ALU has been design based on the proposed gates.

cs.ET↗

arXiv2017

MorphoNoC: Exploring the Design Space of a Configurable Hybrid NoC using Nanophotonics

As diminishing feature sizes drive down the energy for computations, the power budget for on-chip communication is steadily rising. Furthermore, the increasing number of cores is placing a huge performance burden on the network-on-chip (NoC) infrastructure. While NoCs are designed as regular architectures that allow scaling to hundreds of cores, the lack of a flexible topology gives rise to higher latencies, lower throughput, and increased energy costs. In this paper, we explore MorphoNoCs - scalable, configurable, hybrid NoCs obtained by extending regular electrical networks with configurable nanophotonic links. In order to design MorphoNoCs, we first carry out a detailed study of the design space for Multi-Write Multi-Read (MWMR) nanophotonics links. After identifying optimum design points, we then discuss the router architecture for deploying them in hybrid electronic-photonic NoCs. We then study explore the design space at the network level, by varying the waveguide lengths and the number of hybrid routers. This affords us to carry out energy-latency trade-offs. For our evaluations, we adopt traces from synthetic benchmarks as well as the NAS Parallel Benchmark suite. Our results indicate that MorphoNoCs can achieve latency improvements of up to 3.0x or energy improvements of up to 1.37x over the base electronic network.

cs.OH↗

arXiv2012

Students Perceptions of the Effectiveness of Discussion Boards What can we get from our students for a freebie point

We investigate how the students think of their experience in a junior 300 level computer science course that uses blackboard as the underlying course management system. The discussion boards in Blackboard are heavily used for programming project support and to foster cooperation among students to answer their questions and concerns. A survey is conducted through blackboard as a voluntary quiz and the student who participated were given a participation point for their effort. The results and the participation were very interesting. We obtained statistics from the answers to the questions. The students also have given us feedback in the form of comments to all questions except for two only. The students have shown understanding, maturity and willingness to participate in pedagogy-enhancing endeavors with the premise that it might help their education and other people education as well.

cs.CY↗