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Abhi Rajagopala

Publications and source records attributed to Abhi Rajagopala.

3 recordsLinked to original sources

ML-Powered FPGA-based Real-Time Quantum State Discrimination Enabling Mid-circuit Measurements

Accurate and timely quantum state discrimination is critical for quantum computing, particularly in protocols requiring mid-circuit measurement (MCM) and conditional feed-forward. While classical state readout in transistors is near-instantaneous, identifying the state of superconducting qubits remains latency-limited and error-prone. Existing approaches rely on post-processing measurement data transferred to host computers, introducing delays on the order of milliseconds -- vastly exceeding the coherence time of quantum states, which typically last only hundreds of microseconds. To bridge this latency gap, we present an in-situ machine learning (ML) inference engine implemented on a field-programmable gate array (FPGA), enabling real-time quantum state discrimination within 40 ns. Our system supports both two-level (qubit) and three-level (qutrit) systems and performs inference directly on digitized readout signals without host-side intervention. This low-latency operation facilitates mid-circuit measurements, where qubit states are measured and reused within a single quantum circuit, and enables real-time conditional operations essential for quantum error correction. Crucially, fast and accurate mid-circuit readout is a prerequisite for implementing practical fault-tolerant error correction, where errors must be detected and corrected within a single circuit cycle to preserve logical state coherence. We validate our system using superconducting transmon devices, demonstrating robust discrimination fidelity across multiple qubit and qutrit channels. Further, we implement a conditional qutrit logic protocol based on FPGA-resident state classification, highlighting the practical benefits of our approach for NISQ-era quantum algorithms and scalable fault-tolerant architectures.

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Distributed Architecture for FPGA-based Superconducting Qubit Control

Quantum circuits utilizing real time feedback techniques (such as active reset and mid-circuit measurement) are a powerful tool for NISQ-era quantum computing. Such techniques are crucial for implementing error correction protocols, and can reduce the resource requirements of certain quantum algorithms. Realizing these capabilities requires flexible, low-latency classical control. We have developed a custom FPGA-based processor architecture for QubiC, an open source platform for superconducting qubit control. Our architecture is distributed in nature, and consists of a bank of lightweight cores, each configured to control a small (1-3) number of signal generator channels. Each core is capable of executing parameterized control and readout pulses, as well as performing arbitrary control flow based on mid-circuit measurement results. We have also developed a modular compiler stack and domain-specific intermediate representation for programming the processor. Our representation allows users to specify circuits using both gate and pulse-level abstractions, and includes high-level control flow constructs (e.g. if-else blocks and loops). The compiler stack is designed to integrate with quantum software tools and programming languages, such as TrueQ, pyGSTi, and OpenQASM3. In this work, we will detail the design of both the processor and compiler stack, and demonstrate its capabilities with a quantum state teleportation experiment using transmon qubits at the LBNL Advanced Quantum Testbed.

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QubiC 2.0: An Extensible Open-Source Qubit Control System Capable of Mid-Circuit Measurement and Feed-Forward

Researchers manipulate and measure quantum processing units via the classical electronics control system. We developed an open-source FPGA-based quantum bit control system called QubiC for superconducting qubits. After a few years of qubit calibration and testing experience on QubiC 1.0, we recognized the need for mid-circuit measurements and feed-forward capabilities to implement advanced quantum algorithms effectively. Moreover, following the development of RFSoC technology, we upgraded the system to QubiC 2.0 on an Xilinx ZCU216 evaluation board and developed all these enriched features. The system uses portable FPGA gateware with a simplified processor to handle commands on-the-fly. For design simplicity and straightforward scaling, we adopted a multi-core distributed architecture, assigning one processor core per qubit. The actual pulses combine the unique pulse envelope and carrier information specified in a command. Each pulse envelope is pre-stored on FPGA's block RAMs, ensuring the speed and reusability during the whole circuit. The pulse parameters including amplitude, phase, and frequency can be updated from pulse to pulse. The software stack is developed in Python, running on both the FPGA's ARM core and host computer via XML-RPC. The quantum circuit can be described in a high-level language, which supports programming at both pulse-level and native-gate level, and includes high-level control flow constructs. The QubiC software stack compiles these quantum programs into binary commands that can be loaded into the FPGA. With Qubic 2.0, we successfully achieved multi-FPGA synchronization in bench tests and demonstrated simplified feed-forward experiments on conditional circuits. The enhanced QubiC system represents a significant step forward in quantum computing, providing researchers with powerful tools to explore and implement advanced quantum algorithms and applications.

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