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Abhinav Mahadevan

Publications and source records attributed to Abhinav Mahadevan.

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GlitchLab: A Hardware-in-the-Loop Optimizer for Physical Fault Injection

Physical fault injection can turn brief hardware disturbances into security failures such as key recovery, authentication bypass, and unintended control flow. Finding effective faults is difficult because many interacting parameters create a large search space, successful settings are sparse and target-dependent, and each hardware attempt provides limited feedback. Under fixed testing time, efficient search is therefore critical for assessing fault sensitivity. We present GlitchLab, an online hardware-in-the-loop platform that treats delay as a timing gate, voltage and pulse duration as severity controls, and hardware outcomes as structured feedback. It implements RL-Q (Q-learning-based reinforcement learning), a structured bandit for discovery, and Structured-Outcome-Based Adaptive Search (SOBAS), a model-based policy for fault reproduction. Both policies find a target fault in every AES, password, and control-flow campaign. On AES and control flow, they require 2-85x fewer attempts and 26-1,237x less time than the baselines; on password, both succeed while the baselines fail within 5,000 attempts. After discovery, SOBAS reproduces faults 7.3-21x more often, while RL-Q identifies 30% more distinct AES settings.

cs.CR

Hardware-in-the-Loop Phase-Aware CNN for Real-Time 5G Channel Estimation

This demo presents real-time AI-based uplink channel-estimation inference using data collected from a hardware-in-the-loop 5G platform. The data-collection setup integrates commercial RF signal generation, programmable channel emulation, an O-RAN Radio Unit, DU emulation, and a lightweight phase-aware convolutional neural network (CNN) that estimates the channel response directly from received DMRS signals. Unlike simulation-only evaluations, the hardware-derived dataset exposes the estimator to practical RF and system-level impairments, including calibration mismatches, synchronization imperfections, quantization effects, phase noise, and implementation-specific nonlinearities. During the demo, attendees will observe real-time CNN inference and channel reconstruction using captured hardware-generated DMRS observations and compare the proposed CNN against Least Squares (LS) and frequency-domain LMMSE baselines. The objective is to showcase a practical AI-native physical-layer inference pipeline that combines hardware-derived 5G data with real-time neural channel estimation for future 5G-Advanced and 6G systems.

eess.SP

Phase-Aware CNN for Real-Time 5G/6G Channel Estimation with Hardware-in-the-loop Validation

In 5G/6G wireless systems, accurate and timely channel estimation is critical to ensure reliable communication under complex, fast-changing radio conditions. This work focuses on pilot-based channel estimation using deep learning to reconstruct both magnitude and phase across the full subcarrier grid, with particular emphasis on evaluation using emulated data collected from an end-to-end O-RAN testbed. The testbed includes hardware in the loop and controlled channel emulation to better reflect deployment conditions beyond pure software simulation. It addresses major limitations in classical estimators such as LS and MMSE, as well as deep learning-based approaches that struggle with phase prediction due to discontinuities at $\pm \pi$, poor generalization to different UE and antenna configurations, and computational inefficiency for real-time deployment. The proposed system combines a phase-aware input encoding using sine and cosine representations with a lightweight Convolutional Neural Network (CNN) architecture. This design achieves high accuracy, stable phase reconstruction, strong generalization across testbed-derived datasets, and real-time inference suitable for edge devices.

eess.SP