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Adrien Renaudineau

Publications and source records attributed to Adrien Renaudineau.

6 recordsLinked to original sources

Forward-only learning in memristor arrays with month-scale stability

Turning memristor arrays from efficient inference engines into systems capable of on-chip learning has proved difficult. Weight updates have a high energy cost and cause device wear, analog states drift, and backpropagation requires a backward pass with reversed signal flow. Here we experimentally demonstrate learning on standard filamentary HfOx/Ti arrays that addresses these challenges with two design choices. First, we rely on forward-only training algorithms in the Forward-Forward family that use only inference-style operations. Second, we use sub-1 V reset-only, single-pulse updates that cut energy and yield stable analog states. We first validate fully in-hardware single-layer learning, where both analog MAC operations and sub-1 V programming updates are performed on chip. We then train two-layer classifiers on an ImageNet-resolution four-class task using a hardware-in-the-loop protocol on arrays up to 8,064 devices: all conductance reads and programming updates are physical, and multilayer MACs are emulated in software from the measured conductances. Two forward-only variants, two-pass supervised Forward-Forward and a single-pass competitive rule, achieve test accuracies of 89.5% and 89.6%, respectively; a reference experiment using backpropagation reaches 90.0%. Across five independent runs per method, these accuracies are indistinguishable within statistical uncertainty. Trained models retain accuracy for at least one month under ambient conditions and remain stable under an aggressive 25 h read-disturb protocol, whereas a matched set-based Write&Verify baseline loses nearly three percentage points of test accuracy. At the array level, sub-1 V reset updates use 460 times less energy than conventional program-and-verify programming and require just 46% more energy than inference-only operation.

cs.ET

Uncertainty-triggered wake-up enables energy-efficient, error-resilient edge AI with memristor front ends

Memristor computing offers a route to low-energy edge AI, but device variability, sensitivity to operating conditions, and system-integration challenges can hinder deployment. Here we show that these limitations can be mitigated by using memristor AI not as the final decision maker but as the ultra-low-power, always-on front end of a heterogeneous inference system. We implement this architecture by coupling a fabricated memristor Bayesian machine to a programmable CPU running a higher-power, higher-accuracy software neural network. The memristor front end acts as a probabilistic screener. When it predicts an abnormal event or produces an ambiguous or invalid output, a dedicated hardware wake-up path activates the CPU, which produces the final decision. We validate this architecture on a heartbeat-classification benchmark by interfacing the fabricated Bayesian machine with an FPGA-based wake-up platform and CPU back end. The resulting uncertainty-triggered wake-up system achieves high final classification accuracy under nominal operation and maintains this accuracy even when the memristor front end is degraded by voltage scaling or reduced programming margins, because unreliable outputs are converted into recoverable wake-up events instead of becoming silent errors. Post-layout analysis of an ASIC implementation shows that average energy is governed primarily by wake-up frequency, providing practical design rules for choosing front-end operating points. These results establish uncertainty-triggered wake-up as a strategy for energy-efficient, error-resilient edge AI.

cs.ET

Intrinsic Annealing in a Hybrid Memristor-Magnetic Tunnel Junction Ising Machine

Hardware implementations of the Ising model offer promising solutions to large-scale optimization tasks. In the literature, various nanodevices have been shown to emulate the spin dynamics for such Ising machines with remarkable effectiveness. Other nanodevices have been shown to implement spin-spin coupling with compact footprint and minimal energy dissipation. However, an ideal Ising machine would associate both types of nanodevices, and they must operate synergistically to support annealing: a progressive reduction of machine stochasticity that allows it to settle to energy minimum. Here, we report an Ising machine that combines two nanotechnologies: memristor crossbar -- storing multi-level couplings -- and stochastic magnetic tunnel junction (SMTJ), acting as thermally driven spins. Because the same read voltage that interrogates the crossbar also biases the SMTJs, increasing this voltage automatically lowers the effective temperature of the machine, providing an intrinsic, nearly circuit-free annealing technique. Operating at zero magnetic field, our prototype consistently reaches the global optimum of a 24-vertex weighted MAX-CUT and a 10-vertex, three-color graph-coloring problem. Given that both nanotechnologies in our demonstrator are CMOS-integrated, this approach is compatible with advanced 3D integration, offering a scalable pathway toward compact, fast, and energy-efficient large-scale Ising solvers.

cs.ET

Energy landscapes of combinatorial optimization in Ising machines

Physics-based Ising machines (IM) have been developed as dedicated processors for solving hard combinatorial optimization problems with higher speed and better energy efficiency. Generally, such systems employ local search heuristics to traverse energy landscapes in searching for optimal solutions. Here, we quantify and address some of the major challenges met by IMs by extending energy-landscape geometry visualization tools known as disconnectivity graphs. Using efficient sampling methods, we visually capture landscapes of problems having diverse structure and hardness manifesting as energetic and entropic barriers for IMs. We investigate energy barriers, local minima, and configuration space clustering effects caused by locality reduction methods when embedding combinatorial problems to the Ising hardware. To this end, we sample disconnectivity graphs of PUBO energy landscapes and their different QUBO mappings accounting for both local minima and saddle regions. We demonstrate that QUBO energy landscape properties lead to the subpar performance for quadratic IMs and suggest directions for their improvement.

cond-mat.dis-nn

Memristor-based hardware and algorithms for higher-order Hopfield optimization solver outperforming quadratic Ising machines

Ising solvers offer a promising physics-based approach to tackle the challenging class of combinatorial optimization problems. However, typical solvers operate in a quadratic energy space, having only pair-wise coupling elements which already dominate area and energy. We show that such quadratization can cause severe problems: increased dimensionality, a rugged search landscape, and misalignment with the original objective function. Here, we design and quantify a higher-order Hopfield optimization solver, with 28nm CMOS technology and memristive couplings for lower area and energy computations. We combine algorithmic and circuit analysis to show quantitative advantages over quadratic Ising Machines (IM)s, yielding 48x and 72x reduction in time-to-solution (TTS) and energy-to-solution (ETS) respectively for Boolean satisfiability problems of 150 variables, with favorable scaling.

cs.ET

A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects

We present an integrated circuit fabricated in a process co-integrating CMOS and hafnium-oxide memristor technology, which provides a prototyping platform for projects involving memristors. Our circuit includes the periphery circuitry for using memristors within digital circuits, as well as an analog mode with direct access to memristors. The platform allows optimizing the conditions for reading and writing memristors, as well as developing and testing innovative memristor-based neuromorphic concepts.

cs.ET