arXiv subjects

Ahmad Azizimanesh

Publications and source records attributed to Ahmad Azizimanesh.

6 recordsLinked to original sources

arXiv2026

20 Second Parity Lifetime in an InAs--Pb Tetron Device

A central promise of topological quantum computing is that increasing the excitation gap improves device performance significantly. Here, we experimentally validate this principle in an InAs--Pb tetron device via interferometric single-shot parity measurements. By replacing aluminum with the higher-gap superconductor lead in our superconductor-semiconductor hybrid devices, we have improved the robustness of our topological phase. In addition, to enable fast and precise bring-up at scale, we have developed an rf measurement technique that resolves low-energy wire-end states and directly measures their energy splitting with $\mu\text{eV}$ precision. We employ this technique to bring up a device in a multi-tetron array and perform parity measurements of one of the tetron's hybrid nanowires (NWs). By controllably switching the wire parity, we observe $h/2e$-periodic bimodal shifts in the quantum capacitance of a quantum dot coupled to the hybrid nanowire in an interference loop. Further time-resolved measurements reveal a characteristic parity switching time of $\sim 20$ s with some instances reaching minute-scale. Such extremely long parity lifetimes are orders of magnitude longer than typical qubit operation times, which are on the order of $\mu\text{s}$. Finally, we discuss potential implications for the fidelity of Pauli measurements.

cond-mat.mes-hall↗

arXiv2025

Distinct Lifetimes for $X$ and $Z$ Loop Measurements in a Majorana Tetron Device

We present a hardware realization and measurements of a tetron qubit device in a superconductor-semiconductor heterostructure. The device architecture contains two parallel superconducting nanowires, which support four Majorana zero modes (MZMs) when tuned into the topological phase, and a trivial superconducting backbone. Two distinct readout interferometers are formed by connecting the superconducting structure to a series of quantum dots. We perform single-shot interferometric measurements of the fermion parity for the two loops, designed to implement Pauli-$X$ and $Z$ measurements of the tetron. Performing repeated single-shot measurements yields two widely separated time scales $τ_X = 14.5\pm 0.3 \, \mathrm{μs}$ and $τ_Z = 12.4\pm 0.4\, \mathrm{ms}$ for parity switches observed in the $X$ and $Z$ measurement loops, which we attribute to intra-wire parity switches and external quasiparticle poisoning, respectively. We estimate assignment errors of $\mathrm{err}^X_a=16\%$ and $\mathrm{err}^Z_a=0.5\%$ for $X$ and $Z$ measurement-based operations, respectively.

cond-mat.mes-hall↗

arXiv2023

Strain Engineering for High-Performance Phase Change Memristors

A new mechanism for memristive switching in 2D materials is through electric-field controllable electronic/structural phase transitions, but these devices have not outperformed status quo 2D memristors. Here, we report a high-performance bipolar phase change memristor from strain engineered multilayer 1T'-MoTe$_{2}$ that now surpasses the performance metrics (on/off ratio, switching voltage, switching speed) of all 2D memristive devices, achieved without forming steps. Using process-induced strain engineering, we directly pattern stressed metallic contacts to induce a semimetallic to semiconducting phase transition in MoTe2 forming a self-aligned vertical transport memristor with semiconducting MoTe$_{2}$ as the active region. These devices utilize strain to bring them closer to the phase transition boundary and achieve ultra-low ~90 mV switching voltage, ultra-high ~10$^8$ on/off ratio, 5 ns switching, and retention of over 10$^5$ s. Engineered tunability of the device switching voltage and on/off ratio is also achieved by varying the single process parameter of contact metal film force (film stress $\times$ film thickness).

physics.app-ph↗

arXiv2023

Moiré Engineering in 2D Heterostructures with Process-Induced Strain

We report deterministic control over moiré superlattice interference pattern in twisted bilayer graphene by implementing designable device-level heterostrain with process-induced strain engineering, a widely used technique in industrial silicon nanofabrication processes. By depositing stressed thin films onto our twisted bilayer graphene samples, heterostrain magnitude and strain directionality can be controlled by stressor film force (film stress x film thickness) and patterned stressor geometry, respectively. We examine strain and moiré interference with Raman spectroscopy through in-plane and moiré-activated phonon mode shifts. Results support systematic C$_{3}$ rotational symmetry breaking and tunable periodicity in moiré superlattices under the application of uniaxial or biaxial heterostrain. Experimental results are validated by molecular statics simulations and density functional theory based first principles calculations. This provides a method to not only tune moiré interference without additional twisting, but also allows for a systematic pathway to explore different van der Waals based moiré superlattice symmetries by deterministic design.

cond-mat.mes-hall↗

arXiv2021

Strain Engineering 2D MoS$_{2}$ with Thin Film Stress Capping Layers

We demonstrate a method to induce tensile and compressive strain into two-dimensional transition metal dichalcogenide (TMDC) MoS$_{2}$ via the deposition of stressed thin films to encapsulate exfoliated flakes. With this technique we can directly engineer MoS$_{2}$ strain magnitude by changing deposited thin film stress, therefore allowing variable strain to be applied on a flake-to-flake level. These thin film stressors are analogous to SiN$_{x}$ based stressors implemented in industrial CMOS processes to enhance Si mobility, suggesting that our concept is highly scalable and may be applied for large-scale integration of strain engineered TMDC devices. We choose optically transparent stressors to allow us to probe MoS$_{2}$ strain through Raman spectroscopy. Combining thickness dependent analyses of Raman peak shifts in MoS$_{2}$ with atomistic simulations, we can explore layer-by-layer strain transfer. MoS$_{2}$ on conventional substrates (SiO$_{2}$, MgO) show strain transfer into the top two layers of multilayer flakes with limited strain transfer to monolayers due to substrate adhesion. To mitigate this limitation, we also explore stressors on van der Waals heterostructures constructed of monolayer (1L) MoS$_{2}$ on hexagonal boron nitride (h-BN). This concept frees the 1L-MoS$_{2}$ allowing for a 0.85$\%$ strain to be applied to the monolayer with a corresponding strain induced bandgap change of 75 meV. By using thin films with higher stress, strain may be engineered to be even higher. Various stressors and deposition methods are considered, showing a stressor material independent transfer of strain that only depends on stressor film force with negligible defects induced into MoS$_{2}$ when thermal evaporation is used.

cond-mat.mes-hall↗

arXiv2019

Strain-Based Room-Temperature Non-Volatile MoTe$_2$ Ferroelectric Phase Change Transistor

The primary mechanism of operation of almost all transistors today relies on electric-field effect in a semiconducting channel to tune its conductivity from the conducting 'on'-state to a non-conducting 'off'-state. As transistors continue to scale down to increase computational performance, physical limitations from nanoscale field-effect operation begin to cause undesirable current leakage that is detrimental to the continued advancement of computing. Using a fundamentally different mechanism of operation, we show that through nanoscale strain engineering with thin films and ferroelectrics (FEs) the transition metal dichalcogenide (TMDC) MoTe$_2$ can be reversibly switched with electric-field induced strain between the 1T'-MoTe$_2$ (semimetallic) phase to a semiconducting MoTe$_2$ phase in a field effect transistor geometry. This alternative mechanism for transistor switching sidesteps all the static and dynamic power consumption problems in conventional field-effect transistors (FETs). Using strain, we achieve large non-volatile changes in channel conductivity (G$_{on}$/G$_{off}$~10$^7$ vs. G$_{on}$/G$_{off}$~0.04 in the control device) at room temperature. Ferroelectric devices offer the potential to reach sub-ns nonvolatile strain switching at the attojoule/bit level, having immediate applications in ultra-fast low-power non-volatile logic and memory while also transforming the landscape of computational architectures since conventional power, speed, and volatility considerations for microelectronics may no longer exist.

physics.app-ph↗