arXiv subjects

Ahsan Aziz

Publications and source records attributed to Ahsan Aziz.

5 recordsLinked to original sources

arXiv2019

A Blockage Model for the Open Area Mm-wave Device-to-Device Environment

A significant portion of the 5th generation of wireless networks will operate in the mm-wave bands. One of the several challenges associated with mm-wave propagation is to overcome shadowing due to signal blockage caused by environmental objects. Particularly susceptible are nodes in a device-to-device network that typically operate at low power and in a blockage prone environment such as crowded open areas. In this work, we provide an insight into the effect of blockages on the signal quality for an open area device-to-device scenario. We propose a blockage model based on the homogeneous Poisson Point Process. The model provides the average signal attenuation as a soft metric that quantifies the extent of blockage. This not only indicates whether the signal is blocked but also measures how much the signal is attenuated due to one or more blockers. The analytical results are confirmed with the help of Monte Carlo simulations for real-world blocker placement in the environment.

cs.IT↗

arXiv2015

Algebraic Solution for Beamforming in Two-Way Relay Systems with Analog Network Coding

We reduce the problem of optimal beamforming for two-way relay (TWR) systems with perfect channel state infomation (CSI) that use analog network coding (ANC) to a pair of algebraic equations in two variables that can be solved inexpensively using numerical methods. The solution has greatly reduced complexity compared to previous exact solutions via semidefinite programming (SDP). Together with the linearized robust solution described in (Aziz and Thron, 2014), it provides a high-performance, low-complexity robust beamforming solution for 2-way relays.

cs.IT↗

arXiv2015

A 2.48Gb/s QC-LDPC Decoder Implementation on the NI USRP-2953R

The increasing data rates expected to be of the order of Gb/s for future wireless systems directly impact the throughput requirements of the modulation and coding subsystems of the physical layer. In an effort to design a suitable channel coding solution for 5G wireless systems, in this brief we present a massively-parallel 2.48Gb/s Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder implementation operating at 200MHz on the NI USRP-2953R, on a single FPGA. The high-level description of the entire massively-parallel decoder was translated to a Hardware Description Language (HDL), namely VHDL, using the algorithmic compiler in the National Instruments LabVIEW Communication System Design Suite (CSDS) in approximately 2 minutes. This implementation not only demonstrates the scalability of our decoder architecture but also, the rapid prototyping capability of the LabVIEW CSDS tools. As per our knowledge, at the time of writing this paper, this is the fastest implementation of a standard compliant QC-LDPC decoder on a USRP using an algorithmic compiler.

cs.AR↗

arXiv2015

Strategies for High-Throughput FPGA-based QC-LDPC Decoder Architecture

We propose without loss of generality strategies to achieve a high-throughput FPGA-based architecture for a QC-LDPC code based on a circulant-1 identity matrix construction. We present a novel representation of the parity-check matrix (PCM) providing a multi-fold throughput gain. Splitting of the node processing algorithm enables us to achieve pipelining of blocks and hence layers. By partitioning the PCM into not only layers but superlayers we derive an upper bound on the pipelining depth for the compact representation. To validate the architecture, a decoder for the IEEE 802.11n (2012) QC-LDPC is implemented on the Xilinx Kintex-7 FPGA with the help of the FPGA IP compiler [2] available in the NI LabVIEW Communication System Design Suite (CSDS) which offers an automated and systematic compilation flow where an optimized hardware implementation from the LDPC algorithm was generated in approximately 3 minutes, achieving an overall throughput of 608Mb/s (at 260MHz). As per our knowledge this is the fastest implementation of the IEEE 802.11n QC-LDPC decoder using an algorithmic compiler.

cs.AR↗

arXiv2014

Very Low-Complexity Algorithms for Beamforming in Two-Way Relay Systems

In this paper, we present a novel solution for optimal beamforming in a two-way relay (TWR) systems with perfect channel state information. The solution makes use of properties of quadratic surfaces to simplify the solution space of the problem to $\mathbb{R}^4$, and enables the formulation of a differential equation that can be solved numerically to obtain the optimal beamforming matrix.

math.OC↗