arXiv subjects

Aida Todri-Sanial

Publications and source records attributed to Aida Todri-Sanial.

At least 19 recordsLinked to original sources

arXiv2026

Evaluation of Power-Clock Waveforms for Positive Feedback Adiabatic Logic in 16 nm FinFET Technology

Adiabatic logic can recover part of the energy stored on load capacitances through quasi-reversible switching, but its waveform-optimized operation in FinFET technology and at multi-GHz frequencies remains underexplored. This work investigates Positive Feedback Adiabatic Logic (PFAL) in the TSMC 16 nm FinFET process. A functionally complete PFAL gate library is designed, verified, and characterised using energy-delay product optimization over power-clock amplitude, frequency, and waveform shape. The power-clock sweep shows that the minimum-energy waveform approaches a triangular shape rather than a conventional trapezoid. The optimized single-gate PFAL cells achieve up to 3.83x lower energy than equivalent static CMOS gates, while sinusoidal excitation improves energy by up to 1.32x compared with trapezoidal excitation and extends the valid operating range. The library is then used to construct larger combinational circuits, including a 2:1 multiplexer, a 4-bit ripple carry adder, and a 4-bit Brent-Kung carry look-ahead adder. The carry look-ahead adder reaches a gain of up to 5.3x compared with the static CMOS energy estimate for the triangular power-clock.

cs.AR↗

arXiv2026

Evaluating Positive Feedback Adiabatic Logic in 16nm FinFET with a Realistic Power-Clock

Adiabatic logic reuses the energy stored on load capacitances through quasi-reversible switching, enabling a lower minimum energy consumption than conventional static CMOS. Yet its practicality in FinFET technologies and at multi-GHz clock rates has yet to be investigated. This work provides a systematic evaluation of Positive Feedback Adiabatic Logic (PFAL) simulated in the TSMC 16nm FinFET process. A set of PFAL standard-cell gates were realised, along with two representative combinational circuits - a 2$\times$2 multiplier and a 4-bit comparator - and compared against static CMOS logic using the energy--delay product (EDP) and the energy advantage metric $η= E_{\mathrm{CMOS}} / E_{\mathrm{PFAL}}$. Transient simulations reveal three sources of non-adiabatic loss: two specific to the PMOS/NMOS latch, threshold-voltage-related loss and a previously unreported redundant charging of the output node and one related to the complexity of PFAL logic trees. The low-threshold Buffer/NOT cell achieves a minimum EDP of $1.23\times10^{-26}$J$\cdot$s at $V_{\mathrm{CLK}} = 0.6$V and $f_{\mathrm{CLK}} = 7.94$GHz, while PFAL preserves an energy benefit over static CMOS of up to roughly $5\times$ at reduced frequencies and elevated supply voltages. A parallel-coupled quadrature voltage-controlled oscillator is designed as a realistic four-phase power-clock generator. With this non-ideal supply, the Buffer/NOT energy stays within $2\%$ of the ideal sinusoidal case at $3$GHz. A loading study quantifies the phase shift and amplitude reduction induced by increasing fan-out. Overall, the results provide a design-oriented evaluation of PFAL in 16nm FinFET and a motivation to exploit adiabatic logic for future low-power system architectures.

cs.AR↗

arXiv2026

Learning rules for complex-valued patterns in networks of oscillators

In this article, we extend learning rules from real binary to complex-valued spins. This formulation allows for a robust and natural representation of grayscale patterns, where spins behave as multi-state neurons and can be stored in a complex-valued weight matrix. We describe a rule that performs better than standard methods, such as Hebbian learning, to encode information in a suitable form for pattern retrieval with networks of oscillators. Since in neural networks it is of interest to have local and incremental learning rules, we prove the extension of a result by Diederich and Opper with our complex-valued spin formulation. We then test the behavior of the associative memory for the system of oscillators under different circumstances for both real-valued, as well as complex-valued correlated and random patterns.

cond-mat.dis-nn↗

arXiv2026

ODEONN: A Digital ODE Solver Architecture for Oscillatory Neural Networks

Oscillatory Neural Networks (ONNs) are an alternative computing paradigm for AI and combinatorial optimization problems. However, digital architectures are often designed for specific applications of ONNs. This work introduces a modular and scalable architecture called ODEONN that is generic to multiple applications of ONNs, and to the best of our knowledge, is the first fully digital ONN to also support complex-valued coupling. Additionally, an approximation of the sine function is introduced that uses half of the hardware resources compared to standard methods. The performance of ODEONN is compared with a full-precision software simulation, where a performance degradation of less than $2\%$ is shown. Therefore, we conclude that the fixed-point quantization and the approximated waveform affect the accuracy of computation by only a small amount. Furthermore, ODEONN shows a 45$\times$ reduction in energy-delay product over the software simulation running on conventional hardware.

cs.AR↗

arXiv2026

Graph Coloring Approach to Solving Sudoku with Oscillatory Neural Networks

Oscillatory Neural Networks (ONNs) present an attractive physics-based computing paradigm rooted in the dynamics of a network of typically fully coupled oscillators aiming to minimize an underlying energy function. In this paper, we propose an ONN-based solver for one well-known constrained combinatorial optimization problem, namely a Sudoku, by formulating the problem as a Graph Coloring problem. By modifying the already existing Graph Coloring solver to a computationally cheaper version and introducing an additional term ensuring the fulfillment of the Sudoku constraints, our solver is shown to significantly outperform the existing HNN- and ONN solvers in terms of accuracy. In particular, we are able to achieve nearly flawless accuracies on $4 \times 4$ as well as rather high accuracies on $9 \times 9$ Sudoku puzzles for different numbers of unknown digits.

cs.LG↗

arXiv2026

General circuit mapping algorithm for neutral atom quantum computers

Neutral atom quantum computers (NAQC) are emerging as a promising, scalable quantum computing platform because of their long qubit coherence, flexible qubit arrangement, and multiqubit gate capabilities. However, circuit execution often requires physically moving qubits, making compilation a critical optimization challenge. We propose a circuit independent mathematical framework built on graph-theoretic combinatorial optimization that determines the minimal number of required qubit transfers. This model captures spatial constraints specific to NAQC platforms with zone-limited gate operations and multi-qubit gates. From this framework, we encode the qubit mapping problem as a nonlinear integer program and solve it using a genetic algorithm, enabling trade-offs between minimizing the total traveled distance and the number of parallel transfer operations. Compared to the state-of-the-art scalable compiler for zoned architectures, our approach consistently finds fewer transfers. Depending on the optimization focus, our method produces shorter traveled distances or fewer parallel transfer operations. This work provides both theoretical guaranties and a practical tool for efficient, architecture-aware quantum circuit compilation. As a result, practitioners can generate hardware-aware mappings that reduce movement-induced errors and better exploit atom transfer parallelism, directly improving execution efficiency on NAQC devices.

quant-ph↗

arXiv2025

Solving Sudoku using oscillatory neural networks

We explore the capabilities of physical computing with Oscillatory Neural Networks (ONN) to solve combinatorial optimization problems. To solve Sudokus with ONNs, we define a novel mapping strategy that utilizes the unique characteristics of the computation paradigm. The problem is encoded through a puzzle specific graph-embedding, which implements the constraints through different subgraphs. These subgraphs are then combined into a single adjacency matrix, which allows the natural dynamics of the phases of coupled oscillators to find a solution to the puzzle. We model the phase dynamics of the ONN by means of the Kuramoto differential equation. This novel approach is then compared to the well-established iterative method to solve Sudoku already used in binary Hopfield networks (HNN). Solving optimization problems typically requires a large amount of energy to solve on conventional hardware. Therefore, we are motivated to explore the mapping of Sudoku from a theoretical point of view to establish the validity of this approach. The simulation results show that the novel ONN mapping outperforms the established HNN methodology.

cond-mat.dis-nn↗

arXiv2025

Lagrange Oscillatory Neural Networks for Constraint Satisfaction and Optimization

Physics-inspired computing paradigms are receiving renewed attention to enhance efficiency in compute-intensive tasks such as artificial intelligence and optimization. Similar to Hopfield neural networks, oscillatory neural networks (ONNs) minimize an Ising energy function that embeds the solutions of hard combinatorial optimization problems. Despite their success in solving unconstrained optimization problems, Ising machines still face challenges with constrained problems as they can become trapped in infeasible local minima. In this paper, we introduce a Lagrange ONN (LagONN) designed to escape infeasible states based on the theory of Lagrange multipliers. Unlike existing oscillatory Ising machines, LagONN employs additional Lagrange oscillators to guide the system towards feasible states in an augmented energy landscape, settling only when constraints are met. Taking the maximum satisfiability problem with three literals as a use case (Max-3-SAT), we harness LagONN's constraint satisfaction mechanism to find optimal solutions for random SATlib instances with up to 200 variables and 860 clauses, which provides a deterministic alternative to simulated annealing for coupled oscillators. We benchmark LagONN with SAT solvers and further discuss the potential of Lagrange oscillators to address other constraints, such as phase copying, which is useful in oscillatory Ising machines with limited connectivity.

cs.ET↗

arXiv2025

Thermodynamics-Inspired Computing with Oscillatory Neural Networks for Inverse Matrix Computation

We describe a thermodynamic-inspired computing paradigm based on oscillatory neural networks (ONNs). While ONNs have been widely studied as Ising machines for tackling complex combinatorial optimization problems, this work investigates their feasibility in solving linear algebra problems, specifically the inverse matrix. Grounded in thermodynamic principles, we analytically demonstrate that the linear approximation of the coupled Kuramoto oscillator model leads to the inverse matrix solution. Numerical simulations validate the theoretical framework, and we examine the parameter regimes that computation has the highest accuracy.

cs.LG↗

arXiv2025

Decoupling Electric Field and Temperature-Driven Atomistic Forming Mechanisms in TaOx/HfO2-Based ReRAMs using Reactive Molecular Dynamics Simulations

Resistive random access memories (ReRAMs) with a bilayer TaOx/HfO2 stack structure have shown unique multi-level resistive switching capabilities. However, the physical processes governing their behavior, and specifically the atomistic mechanisms of forming, remain poorly understood. In this work, we present a detailed analysis of the forming mechanism at the atomic level using molecular dynamics (MD) simulations. An extended charge equilibration scheme, based on a combination of the charge transfer ionic potential (CTIP) formalism and the electrochemical dynamics with implicit degrees of freedom (EChemDID) method, is employed to model the localized effects of applied voltage. Our simulations reveal that tantalum ions exhibit the highest displacement under applied voltage, followed by hafnium ions, while oxygen ions respond only minimally. This results in the formation of a tantalum-depleted, oxygen-rich zone near the positive top electrode (anode), and the clustering of oxygen vacancies near the negative bottom electrode (cathode), where the conductive filament nucleates. This ionic segregation partially shields the bulk dielectric from the applied electric field, hindering further migration of ions in the vertical direction. We find that a minimum threshold voltage is required to initiate vacancy clustering. Filament growth proceeds through a localized mechanism, driven by thermally activated generation of oxygen vacancy defects, which are stabilized near the edge of the nucleated filament at the cathode.

cond-mat.mtrl-sci↗

arXiv2025

Overcoming Quadratic Hardware Scaling for a Fully Connected Digital Oscillatory Neural Network

Computing with coupled oscillators or oscillatory neural networks (ONNs) has recently attracted a lot of interest due to their potential for massive parallelism and energy-efficient computing. However, to date, ONNs have primarily been explored either analytically or through analog circuit implementations. This paper shifts the focus to the digital implementation of ONNs, examining various design architectures. We first report on an existing digital ONN design based on a recurrent architecture. The major challenge for scaling such recurrent architectures is the quadratic increase in coupling hardware with the network size. To overcome this challenge, we introduce a novel hybrid architecture that balances serialization and parallelism in the coupling elements that shows near-linear hardware scaling, on the order of about 1.2 with the network size. Furthermore, we evaluate the benefits and costs of these different digital ONN architectures in terms time to solution and resource usage on FPGA emulation. The proposed hybrid architecture allows for a 10.5$\times$ increase in the number of oscillators while using 5-bits to represent the coupling weights and 4-bits to represent the oscillator phase on a Zynq-7020 FPGA board. The near-linear scaling is a major step towards implementing large scale ONN architectures. To the best of our knowledge, this work presents the largest fully connected digital ONN architecture implemented thus far with a total of 506 fully connected oscillators.

cs.AR↗

arXiv2025

Hardware Implementation of Ring Oscillator Networks Coupled by BEOL Integrated ReRAM for Associative Memory Tasks

We demonstrate the first hardware implementation of an oscillatory neural network (ONN) utilizing resistive memory (ReRAM) for coupling elements. A ReRAM crossbar array chip, integrated into the Back End of Line (BEOL) of CMOS technology, is leveraged to establish dense coupling elements between oscillator neurons, allowing phase-encoded analog information to be processed in-memory. We also realize an ONN architecture design with the coupling ReRAM array. To validate the architecture experimentally, we present a conductive metal oxide (CMO)/HfOx ReRAM array chip integrated with a 2-by-2 ring oscillator-based network. The system successfully retrieves patterns through correct binary phase locking. This proof of concept underscores the potential of ReRAM technology for large-scale, integrated ONNs.

cs.ET↗

arXiv2024

Multi-qubit Dynamical Decoupling for Enhanced Crosstalk Suppression

Dynamical decoupling (DD) is one of the simplest error suppression methods, aiming to enhance the coherence of qubits in open quantum systems. Moreover, DD has demonstrated effectiveness in reducing coherent crosstalk, one major error source in near-term quantum hardware, which manifests from two types of interactions. Static crosstalk exists in various hardware platforms, including superconductor and semiconductor qubits, by virtue of always-on qubit-qubit coupling. Additionally, driven crosstalk may occur as an unwanted drive term due to leakage from driven gates on other qubits. Here we explore a novel staggered DD protocol tailored for multi-qubit systems that suppresses the decoherence error and both types of coherent crosstalk. We develop two experimental setups -- an "idle-idle" experiment in which two pairs of qubits undergo free evolution simultaneously and a "driven-idle" experiment in which one pair is continuously driven during the free evolution of the other pair. These experiments are performed on an IBM Quantum superconducting processor and demonstrate the significant impact of the staggered DD protocol in suppressing both types of coherent crosstalk. When compared to the standard DD sequences from state-of-the-art methodologies with the application of X2 sequences, our staggered DD protocol enhances circuit fidelity by 19.7% and 8.5%, respectively, in addressing these two crosstalk types.

quant-ph↗

arXiv2024

Conductive metal oxide and hafnium oxide bilayer ReRAM: an ab initio study

We perform generalized gradient approximation (GGA) simulations of interfaces between two Conductive Metal-Oxides (CMO, namely TaO and TiO) and cubic hafnium oxide ($HfO_2$) in the context of bilayer Resistive Random Access Memory (ReRAM) devices. We simulate filamentary conduction in $HfO_2$ by creating an atomically thin O atom vacancy path inside $HfO_2$. We show that this atomically thin filament leads to a great reduction of the resistance of the structures. Moreover, we explore the possibility of the influence of O excess inside the CMO on the global resistance of the device and confirm the induced modulation. We also shed the light on two possible causes for the observed increas in the resistance when O atoms are inserted inside the CMO. Eventually, we push forward key differences between devices with TaO and TiO as CMO. We show that structures with TaO are more stable in general and lead to a behaviour implying only low and high resistance (two well separated levels) while structures with TiO allows for intermediate resistances.

cond-mat.mtrl-sci↗

arXiv2024

Roadmap for Unconventional Computing with Nanotechnology

In the "Beyond Moore's Law" era, with increasing edge intelligence, domain-specific computing embracing unconventional approaches will become increasingly prevalent. At the same time, adopting a variety of nanotechnologies will offer benefits in energy cost, computational speed, reduced footprint, cyber resilience, and processing power. The time is ripe for a roadmap for unconventional computing with nanotechnologies to guide future research, and this collection aims to fill that need. The authors provide a comprehensive roadmap for neuromorphic computing using electron spins, memristive devices, two-dimensional nanomaterials, nanomagnets, and various dynamical systems. They also address other paradigms such as Ising machines, Bayesian inference engines, probabilistic computing with p-bits, processing in memory, quantum memories and algorithms, computing with skyrmions and spin waves, and brain-inspired computing for incremental learning and problem-solving in severely resource-constrained environments. These approaches have advantages over traditional Boolean computing based on von Neumann architecture. As the computational requirements for artificial intelligence grow 50 times faster than Moore's Law for electronics, more unconventional approaches to computing and signal processing will appear on the horizon, and this roadmap will help identify future needs and challenges. In a very fertile field, experts in the field aim to present some of the dominant and most promising technologies for unconventional computing that will be around for some time to come. Within a holistic approach, the goal is to provide pathways for solidifying the field and guiding future impactful discoveries.

cs.ET↗

arXiv2023

Enabling Multi-programming Mechanism for Quantum Computing in the NISQ Era

NISQ devices have several physical limitations and unavoidable noisy quantum operations, and only small circuits can be executed on a quantum machine to get reliable results. This leads to the quantum hardware under-utilization issue. Here, we address this problem and improve the quantum hardware throughput by proposing a Quantum Multi-programming Compiler (QuMC) to execute multiple quantum circuits on quantum hardware simultaneously. This approach can also reduce the total runtime of circuits. We first introduce a parallelism manager to select an appropriate number of circuits to be executed at the same time. Second, we present two different qubit partitioning algorithms to allocate reliable partitions to multiple circuits - a greedy and a heuristic. Third, we use the Simultaneous Randomized Benchmarking protocol to characterize the crosstalk properties and consider them in the qubit partition process to avoid the crosstalk effect during simultaneous executions. Finally, we enhance the mapping transition algorithm to make circuits executable on hardware using a decreased number of inserted gates. We demonstrate the performance of our QuMC approach by executing circuits of different sizes on IBM quantum hardware simultaneously. We also investigate this method on VQE algorithm to reduce its overhead.

cs.AR↗

arXiv2022

Effects of Dynamical Decoupling and Pulse-level Optimizations on IBM Quantum Computers

Currently available quantum computers are prone to errors. Circuit optimization and error mitigation methods are needed to design quantum circuits to achieve better fidelity when executed on NISQ hardware. Dynamical decoupling (DD) is generally used to suppress the decoherence error and different DD strategies have been proposed. Moreover, the circuit fidelity can be improved by pulse-level optimization, such as creating hardware-native pulse-efficient gates. This paper implements all the popular DD sequences and evaluates their performances on IBM quantum chips with different characteristics for various well-known quantum applications. Also, we investigate combining DD with pulse-level optimization method and apply them to QAOA to solve Max-Cut problem. Based on the experimental results, we found that DD can be a benefit for only certain types of quantum algorithms, while the combination of DD and pulse-level optimization methods always has a positive impact. Finally, we provide several guidelines for users to learn how to use these noise mitigation methods to build circuits for quantum applications with high fidelity on IBM quantum computers.

quant-ph↗

arXiv2022

Multi-programming Cross Platform Benchmarking for Quantum Computing Hardware

With the rapid development of quantum hardware technologies, benchmarking the performance of quantum computers has become attractive. In this paper, we propose a new aspect of benchmarking quantum computers by evaluating the limitation of hardware utilization using a multi-programming mechanism -- a technique that simultaneously executes multiple circuits in a quantum machine. This is the first attempt to compare the evaluation of multi-programming on trapped-ion and superconducting devices. Based on the experimental results, performing multi-programming on a trapped-ion device demonstrates better results than a superconducting machine without losing any fidelity to independent executions.

quant-ph↗