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Alena S. Kazmina

Publications and source records attributed to Alena S. Kazmina.

5 recordsLinked to original sources

Interleaved Benchmarking with Single-Qubit References

Cross-entropy benchmarking (XEB) with single-qubit reference sequences is widely used to characterize multi-qubit gates in large-scale quantum processors, despite the lack of a rigorous theoretical justification. Here we show that the commonly employed additive single-qubit errors approximation underlying this approach breaks down and leads to a systematic overestimation of gate fidelities. We derive an analytical expression for the joint decay of simultaneous single-qubit reference sequences, identify when interleaved circuits generate sufficient randomization for the standard depolarizing approximation, and obtain a refined expression for the interleaved gate fidelity estimation. Experiments on a superconducting quantum processor validate the theory and demonstrate that fidelities obtained using XEB with single-qubit references agree with those extracted from standard interleaved randomized benchmarking (IRB), while achieving higher precision due to reduced reference-sequence errors. Our results establish theoretical foundation for interleaved benchmarking protocols employing single-qubit reference sequences and show that, with appropriate post-processing, they provide a simple and accurate alternative to multi-qubit Clifford reference circuits.

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Native CCZ Gate with Fluxonium Qubits and a Microwave-Driven Coupler

Native multi-qubit gates could reduce the overhead associated with decompositions into single- and two-qubit operations, but whether they can simultaneously provide high fidelity, simple control and robustness against parasitic interactions in scalable architectures remains unclear. Here we experimentally realize a 65-ns native controlled-controlled-phase operation, locally equivalent to the Toffoli gate, with a fidelity of 99.39(5)% in a three-qubit processor unit based on fluxonium qubits coupled via a microwave-driven transmon coupler. The implemented operation would require CZ fidelities of approximately 99.94% if realized through a conventional decomposition. The gate is implemented with a single control pulse, that relies on a simple calibration procedure yielding coherence-limited performance. This processor unit naturally extends to scalable two-dimensional layouts with low parasitic interactions. Altogether, these results establish native multi-qubit gates as a viable hardware-efficient primitive for scalable superconducting quantum processors.

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Realization of a Quantum Error Detection Code with a Dynamically Reassigned Ancillary Qubit

Quantum error correction (QEC) is essential for achieving fault-tolerant quantum computing. While superconducting qubits are among the most promising candidates for scalable QEC, their limited nearest-neighbor connectivity presents significant challenges for implementing a wide range of error correction codes. In this work, we experimentally demonstrate a quantum error detection scheme that employs a dynamically reassigned ancillary qubit on a chain of three linearly connected transmon qubits. We show that this scheme achieves performance comparable to conventional static-ancilla circuits. Additionally, the approach facilitates efficient quantum state preparation, which we demonstrate with tomography of arbitrary logical states. Our results provide a flexible method for implementing QEC codes under connectivity constraints and highlight a promising path toward scalable quantum architectures.

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Three-mode tunable coupler for superconducting two-qubit gates

Building a scalable universal high-performance quantum processor is a formidable challenge. In particular, the problem of realizing fast high-perfomance two-qubit gates of high-fidelity remains needful. Here we propose a building block for a scalable quantum processor consisting of two transmons and a tunable three-mode coupler allowing for a ZZ interaction control. We experimentally demonstrate the native CZ gate with the pulse duration of 60 ns achieving the two-qubit gate fidelity above 98%, limited mostly by qubit coherence time. Numerical simulations show that by optimizing the gate duration the fidelity can be pushed over 99.97%.

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Demonstration of a parity-time symmetry breaking phase transition using superconducting and trapped-ion qutrits

Scalable quantum computers hold the promise to solve hard computational problems, such as prime factorization, combinatorial optimization, simulation of many-body physics, and quantum chemistry. While being key to understanding many real-world phenomena, simulation of non-conservative quantum dynamics presents a challenge for unitary quantum computation. In this work, we focus on simulating non-unitary parity-time symmetric systems, which exhibit a distinctive symmetry-breaking phase transition as well as other unique features that have no counterpart in closed systems. We show that a qutrit, a three-level quantum system, is capable of realizing this non-equilibrium phase transition. By using two physical platforms -- an array of trapped ions and a superconducting transmon -- and by controlling their three energy levels in a digital manner, we experimentally simulate the parity-time symmetry-breaking phase transition. Our results indicate the potential advantage of multi-level (qudit) processors in simulating physical effects, where additional accessible levels can play the role of a controlled environment.

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