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Alessio Martino

Publications and source records attributed to Alessio Martino.

2 recordsLinked to original sources

Structural properties of distance-bounded phylogenetic reconciliation

Phylogenetic reconciliation seeks to explain host-symbiont co-evolution by mapping parasite trees onto host trees through events such as cospeciation, duplication, host switching, and loss. Finding an optimal reconciliation that ensures time feasibility is computationally hard when timing information is incomplete, and the complexity remains open when host switches are restricted by a fixed maximum distance $d$. While the case $d=2$ is known to be polynomial, larger values are unresolved. In this paper, we study the cases $d=3$ and $d=4$. We show that although arbitrarily large cycles may occur, it suffices to check only bounded-size cycles (we provide a complete list), provided the reconciliation satisfies acyclicity (i.e., time-feasibility) in a stronger sense. These results do not resolve the general complexity, but highlight structural properties that advance the understanding of distance-bounded reconciliations.

q-bio.PE

A novel algorithm for online inexact string matching and its FPGA implementation

Accelerating inexact string matching procedures is of utmost importance when dealing with practical applications where huge amount of data must be processed in real time, as usual in bioinformatics or cybersecurity. Inexact matching procedures can yield multiple shadow hits, which must be filtered, according to some criterion, to obtain a concise and meaningful list of occurrences. The filtering procedures are often computationally demanding and are performed offline in a post-processing phase. This paper introduces a novel algorithm for Online Approximate String Matching (OASM) able to filter shadow hits on the fly, according to general purpose priority rules that greedily assign priorities to overlapping hits. An FPGA hardware implementation of OASM is proposed and compared with a serial software version. Even when implemented on entry level FPGAs, the proposed procedure can reach a high degree of parallelism and superior performance in time compared to the software implementation, while keeping low the usage of logic elements. This makes the developed architecture very competitive in terms of both performance and cost of the overall computing system.

cs.DC