arXiv subjects

Alex Wynn

Publications and source records attributed to Alex Wynn.

13 recordsLinked to original sources

arXiv2026

Elimination of Flux Trapping in Superconducting Circuits in Ambient Magnetic Fields

Superconductor digital electronics and quantum computing with superconducting qubits are promising next-generation computing technologies. When cooled down or operated in the presence of a nonzero background magnetic field $B_r$, superconducting thin films comprising the circuits can trap magnetic vortices that can degrade circuit or qubit performance. In this work, we report a practical solution for eliminating flux trapped during cooldown in ambient magnetic fields, $B_r\leq 60$ $\upmu$T, based on controlled local thermal gradients and moats, etched holes in the superconducting films of the circuit. Thermal gradients created by integrated on-chip resistive heaters move vortices towards the moats, where they become trapped away from circuitry regions and pinning sites. Using magnetic imaging and electrical circuit readout, we demonstrate that this approach is capable of removing magnetic flux trapped during field cooling and magnetic flux nucleated by circuit operation. If used in an environment with basic magnetic shielding, this solution is capable of suppressing all magnetic flux in a large-scale circuit, overcoming one of the long-standing challenges preventing high-performance scalable computing using superconductors.

cond-mat.supr-con↗

arXiv2026

Mitigation of Magnetic Flux Trapping in Superconducting Electronics Using Moats

Magnetic flux (vortex) trapping remains a major obstacle to very large scale integration in superconducting electronics. Moats -- etched regions in circuit layers placed in ground planes and around critical circuitry -- offer a simple passive approach to sequester flux. Here, we systematically examine the effectiveness of moat arrays in superconducting niobium films as a function of geometry (size, shape, and density) and background magnetic field. By measuring the vortex expulsion field, we estimate the flux saturation number and flux trapping temperature for a range of geometries. We find that many moat designs effectively sequester flux in magnetically shielded environments (< 1 $\mu$T), with high-aspect-ratio rectangular "slit" moats providing the strongest mitigation at minimal area cost. However, our measurements show that moats alone do not eliminate flux trapping in non-ideal films, as vortices can preferentially pin at material defects. These results provide design guidance for flux mitigation in superconducting integrated circuits and highlight the need for combined optimization of circuit geometries and materials.

cond-mat.supr-con↗

arXiv2025

Flux-trapping characterization for superconducting electronics using a cryogenic widefield N-$V$ diamond microscope

Magnetic flux trapping is a significant hurdle limiting the reliability and scalability of superconducting electronics, yet tools for imaging flux vortices remain slow or insensitive. We present a cryogenic widefield NV-diamond magnetic microscope capable of rapid, micrometer-scale imaging of flux trapping in superconducting devices. Using this technique, we measure vortex expulsion fields in Nb thin films and patterned strips, revealing a crossover in expulsion behavior between $10$ and $20~\mu$m strip widths. The observed scaling agrees with theoretical models and suggests the influence of film defects on vortex expulsion dynamics. This instrument enables high-throughput magnetic characterization of superconducting materials and circuits, providing new insight for flux mitigation strategies in scalable superconducting electronics.

cond-mat.supr-con↗

arXiv2023

Extremely Large Area (88 mm X 88 mm) Superconducting Integrated Circuit (ELASIC)

Superconducting integrated circuit (SIC) is a promising "beyond-CMOS" device technology enables speed-of-light, nearly lossless communications to advance cryogenic (4 K or lower) computing. However, the lack of large-area superconducting IC has hindered the development of scalable practical systems. Herein, we describe a novel approach to interconnect 16 high-resolution deep UV (DUV EX4, 248 nm lithography) full reticle circuits to fabricate an extremely large (88mm X 88 mm) area superconducting integrated circuit (ELASIC). The fabrication process starts by interconnecting four high-resolution DUV EX4 (22 mm X 22 mm) full reticles using a single large-field (44 mm X 44 mm) I-line (365 nm lithography) reticle, followed by I-line reticle stitching at the boundaries of 44 mm X 44 mm fields to fabricate the complete ELASIC field (88 mm X 88 mm). The ELASIC demonstrated a 2X-12X reduction in circuit features and maintained high-stitched line superconducting critical currents. We examined quantum flux parametron (QFP) circuits to demonstrate the viability of common active components used for data buffering and transmission. Considering that no stitching requirement for high-resolution EX4 DUV reticles is employed, the present fabrication process has the potential to advance the scaling of superconducting quantum devices.

cond-mat.supr-con↗

arXiv2022

Low-Cost Superconducting Fan-Out with Cell I$_\text{C}$ Ranking

Superconductor electronics (SCE) promise computer systems with orders of magnitude higher speeds and lower energy consumption than their complementary metal-oxide semiconductor (CMOS) counterparts. At the same time, the scalability and resource utilization of superconducting systems are major concerns. Some of these concerns come from device-level challenges and the gap between SCE and CMOS technology nodes, and others come from the way Josephson Junctions (JJs) are used. Towards this end, we notice that a considerable fraction of hardware resources are not involved in logic operations, but rather are used for fan-out and buffering purposes. In this paper, we ask if there is a way to reduce these overheads, propose the use of JJs at the cell boundaries to increase the number of outputs that a single stage can drive, and establish a set of rules to discretize critical currents in a way that is conducive to this assignment. Finally, we explore the design trade-offs that the presented approach opens up and demonstrate its promise through detailed analog simulations and modeling analyses. Our experiments indicate that the introduced method leads to a 48% savings in the JJ count for a tree with a fan-out of 1024, as well as an average of 43% of the JJ count for signal splitting and 32% for clock splitting in ISCAS'85 benchmarks.

cs.ET↗

arXiv2022

Addressable Superconductor Integrated Circuit Memory from Delay Lines

Recent advances in logic schemes and fabrication processes have renewed interest in using superconductor electronics for energy-efficient computing and quantum control processors. However, scalable superconducting memory still poses a challenge. To address this issue, we present an alternative to approaches that solely emphasize storage cell miniaturization by exploiting the minimal attenuation and dispersion properties of superconducting passive transmission lines to develop a delay-line memory system. This fully superconducting design operates at speeds between 20 GHz and 100 GHz, with $\pm$24\% and $\pm$13\% bias margins, respectively, and demonstrates data densities in the 10s of Mbit/cm$^2$ with the MIT Lincoln Laboratory SC2 fabrication process. Additionally, the circulating nature of this design allows for minimal control circuitry, eliminates the need for data splitting and merging, and enables inexpensive implementations of sequential access and content-addressable memories. Further advances in fabrication processes suggest data densities of 100s of Mbit/cm$^2$ and beyond

cs.ET↗

arXiv2021

Wafer-Scale Characterization of a Superconductor Integrated Circuit Fabrication Process, Using a Cryogenic Wafer Prober

Using a fully automated cryogenic wafer prober, we measured superconductor fabrication process control monitors and simple integrated circuits on 200 mm wafers at 4.4 K, including SQIF-based magnetic field sensors, SQUID-based circuits for measuring inductors, Nb/Al-AlOx/Nb Josephson junctions, test structures for measuring critical current of superconducting wires and vias, resistors, etc., to demonstrate the feasibility of using the system for characterizing niobium superconducting devices and integrated circuits on a wafer scale. Data on the wafer-scale distributions of the residual magnetic field, junction tunnel resistance, energy gap, inductance of multiple Nb layers, critical currents of interlayer vias are presented. Comparison with existing models is made. The wafers were fabricated in the SFQ5ee process, the fully planarized process with eight niobium layers and a layer of kinetic inductors, developed for superconductor electronics at MIT Lincoln Laboratory. The cryogenic wafer prober was developed at HPD/ FormFactor, Inc.

cond-mat.supr-con↗

arXiv2019

Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS π-Junctions

We present our new fabrication Process for Superconductor Electronics (PSE2) that integrates two (2) layers of Josephson junctions in a fully planarized multilayer process on 200-mm wafers. The two junction layers can be, e.g., conventional Superconductor-Insulator-Superconductor (SIS) Nb/Al/AlO_x/Nb junctions with the same or different Josephson critical current densities, J_c. The process also allows integration of high-J_c Superconductor-Ferromagnet-Superconductor (SFS) or SFS'S JJs on the first junction layer with Nb/Al/AlO_x/Nb trilayer junctions on the second junction layer, or vice versa. In the present node, the SFS trilayer, Nb/Ni/Nb is placed below the standard SIS trilayer and separated by one niobium wiring layer. The main purpose of integrating the SFS and SIS junction layers is to provide compact π-phase shifters in logic cells of superconductor digital circuits and random access memories, and thereby increase the integration scale and functional density of superconductor electronics. The current node of the two-junction-layer process has six planarized niobium layers, two layers of resistors, and 350-nm minimum feature size. The target Josephson critical current densities for the SIS junctions are 100 μA/μm^2 and 200 μA/μm^2. We present the salient features of the new process, fabrication details, and characterization results on two layers of Josephson junctions integrated into one process, both for the conventional and π-junctions.

cond-mat.supr-con↗

arXiv2018

Superconductor Electronics Fabrication Process with MoN$_x$ Kinetic Inductors and Self-Shunted Josephson Junctions

Recent progress in superconductor electronics fabrication has enabled single-flux-quantum (SFQ) digital circuits with close to one million Josephson junctions (JJs) on 1-cm$^2$ chips. Increasing the integration scale further is challenging because of the large area of SFQ logic cells, mainly determined by the area of resistively shunted Nb/AlO$_x$-Al/Nb JJs and geometrical inductors utilizing multiple layers of Nb. To overcome these challenges, we are developing a fabrication process with self-shunted high-J$_c$ JJs and compact thin-film MoN$_x$ kinetic inductors instead of geometrical inductors. We present fabrication details and properties of MoN$_x$ films with a wide range of T$_c$, including residual stress, electrical resistivity, critical current, and magnetic field penetration depth λ$_0$. As kinetic inductors, we implemented Mo$_2$N films with T$_c$ about 8 K, λ$_0$ about 0.51 μm, and inductance adjustable in the range from 2 to 8 pH/sq. We also present data on fabrication and electrical characterization of Nb-based self-shunted JJs with AlO$_x$ tunnel barriers and J$_c$ = 0.6 mA/μm$^2$, and with 10-nm thick Si$_{1-x}$Nb$_x$ barriers, with x from 0.03 to 0.15, fabricated on 200-mm wafers by co-sputtering. We demonstrate that the electron transport mechanism in Si$_{1-x}$Nb$_x$ barriers at x < 0.08 is inelastic resonant tunneling via chains of multiple localized states. At larger x, their Josephson characteristics are strongly dependent on x and residual stress in Nb electrodes, and in general are inferior to AlO$_x$ tunnel barriers.

cond-mat.supr-con↗

arXiv2017

Developments Toward a 250-nm, Fully Planarized Fabrication Process With Ten Superconducting Layers And Self-Shunted Josephson Junctions

We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. The minimum feature size of resistors and inductors in the process is 250 nm. We present data on the mutual inductance of Nb stripline and microstrip inductors with linewidth and spacing from 250 nm to 1 μm made on the same or adjacent Nb layers, as well as the data on the linewidth and resistance uniformity.

cond-mat.supr-con↗

arXiv2017

Properties of Unshunted and Resistively Shunted Nb/AlOx-Al/Nb Josephson Junctions With Critical Current Densities from 0.1 mA/μm^2 to 1 mA/μm^2

We investigated current-voltage characteristics of unshunted and externally shunted Josephson junctions (JJs) with high critical current densities, Jc, in order to extract their basic parameters and statistical characteristics for JJ modeling in superconducting integrated circuits and to assess their potential for future technology nodes. Nb/AlOx-Al/Nb JJs with diameters from 0.5 μm to 6 μm were fabricated using a fully planarized process with Mo or MoNx thin-film shunt resistors with sheet resistance Rsq = 2 Ω/sq and Rsq = 6 Ω/sq, respectively. We used our standard MIT LL process SFQ5ee to fabricate JJs with Jc = 0.1 mA/μm^2 and our new process SFQ5hs to make JJs with Jc = 0.2 mA/μm^2 and higher current densities up to about 1 mA/μm^2. Using LRC resonance features on the I-V characteristics of shunted JJs, we extract the inductance associated with molybdenum shunt resistors of 1.4 pH/sq. The main part this inductance, about 1.1 pH/sq, is the inductance of the 40-nm Mo resistor film, while the geometrical inductance of superconducting Nb wiring contributes the rest. We attribute this large inductance to kinetic inductance arising from the complex conductivity of a thin normal-metal film in an electromagnetic field with angular frequency ω, σ(ω)=σ0/(1+iωτ), where σ0 is the static conductivity and τ the electron scattering time. Using a resonance in a large-area unshunted high-Jc junction excited by a resistively coupled small-area shunted JJ, we extract the Josephson plasma frequency and specific capacitance of high-Jc junctions in 0.1 to 1 mA/μm^2 Jc range. We also present data on Jc targeting and JJ critical current spreads. We discuss using 0.2-mA/μm^2 JJs in VLSI Single Flux Quantum circuits and 0.5-mA/μm^2 JJs in high-density integrated circuits without shunt resistors.

cond-mat.supr-con↗

arXiv2016

Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits

We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating Single Flux Quantum(SFQ) digital circuits with very large scale integration on 200-mm wafers: the SFQ4ee and SFQ5ee nodes, where 'ee' denotes the process is tuned for energy efficient SFQ circuits. The former has eight superconducting layers with 0.5 μm minimum feature size and a 2 Ω/sq Mo layer for circuit resistors. The latter has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm and a thin superconducting MoNx layer (Tc ~ 7.5 K) with high kinetic inductance (about 8 pH/sq) for forming compact inductors. A nonsuperconducting (Tc < 2 K) MoNx layer with lower nitrogen content is used for 6 Ω/sq planar resistors for shunting and biasing of Josephson junctions. Another resistive layer is added to form interlayer, sandwich-type resistors of mΩ range for releasing unwanted flux quanta from superconducting loops of logic cells. Both process nodes use Au/Pt/Ti contact metallization for chip packaging. The technology utilizes one layer of Nb/AlOx-Al/Nb JJs with critical current density, Jc of 100 μA/μm^2 and minimum diameter of 700 nm. Circuit patterns are defined by 248-nm photolithography and high density plasma etching. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO2 interlayer dielectric. The following results and topics are presented and discussed: the effect of surface topography under the JJs on the their properties and repeatability, critical current and Jc targeting, effect of hydrogen dissolved in Nb, MoNx properties for the resistor layer and for high kinetic inductance layer, technology of mΩ-range resistors.

cond-mat.supr-con↗

arXiv2015

Electrical control of near-field energy transfer between quantum dots and 2D semiconductors

We investigate near-field energy transfer between chemically synthesized quantum dots (QDs) and two-dimensional semiconductors. We fabricate devices in which electrostatically gated semiconducting monolayer molybdenum disulfide (MoS2) is placed atop a homogenous self-assembled layer of core-shell CdSSe QDs. We demonstrate efficient non-radiative Förster resonant energy transfer (FRET) from QDs into MoS2 and prove that modest gate-induced variation in the excitonic absorption of MoS2 lead to large (~500%) changes in the FRET rate. This, in turn, allows for up to ~75% electrical modulation of QD photoluminescence intensity. The hybrid QD/MoS2 devices operate within a small voltage range, allow for continuous modification of the QD photoluminescence intensity, and can be used for selective tuning of QDs emitting in the visible-IR range.

cond-mat.mes-hall↗