arXiv subjects

Alexandru Paler

Publications and source records attributed to Alexandru Paler.

At least 55 records · Page 3Linked to original sources

arXiv2021

Halving the width of Toffoli based constant modular addition to n+3 qubits

We present an arithmetic circuit performing constant modular addition having $\mathcal{O}(n)$ depth of Toffoli gates and using a total of $n+3$ qubits. This is an improvement by a factor of two compared to the width of the state-of-the-art Toffoli-based constant modular adder. The advantage of our adder, compared to the ones operating in the Fourier-basis, is that it does not require small angle rotations and their Clifford+T decomposition. Our circuit uses a recursive adder combined with the modular addition scheme proposed by Vedral et. al. The circuit is implemented and verified exhaustively with QUANTIFY, an open-sourced framework. We also report on the Clifford+T cost of the circuit.

quant-ph↗

arXiv2021

On the realistic worst case analysis of quantum arithmetic circuits

We provide evidence that commonly held intuitions when designing quantum circuits can be misleading. In particular we show that: a) reducing the T-count can increase the total depth; b) it may be beneficial to trade CNOTs for measurements in NISQ circuits; c) measurement-based uncomputation of relative phase Toffoli ancillae can make up to 30\% of a circuit's depth; d) area and volume cost metrics can misreport the resource analysis. Our findings assume that qubits are and will remain a very scarce resource. The results are applicable for both NISQ and QECC protected circuits. Our method uses multiple ways of decomposing Toffoli gates into Clifford+T gates. We illustrate our method on addition and multiplication circuits using ripple-carry. As a byproduct result we show systematically that for a practically significant range of circuit widths, ripple-carry addition circuits are more resource efficient than the carry-lookahead addition ones. The methods and circuits were implemented in the open-source QUANTIFY software.

quant-ph↗

arXiv2020

OpenSurgery for Topological Assemblies

Surface quantum error-correcting codes are the leading proposal for fault-tolerance within quantum computers. We present OpenSurgery, a scalable tool for the preparation of circuits protected by the surface code operated through lattice surgery. Lattice surgery is considered a resource efficient method to implement surface code computations. Resource efficiency refers to the number of physical qubits and the time necessary for executing a quantum computation. OpenSurgery is a first step towards methods that aid quantum algorithm design informed by the realities of the hardware architectures. OpenSurgery can: 1) lay out arbitrary quantum circuits, 2) estimate the quantum resources used for their execution, 3) visualise the resulting 3D topological assemblies. Source code is available at http://www.github.com/alexandrupaler/opensurgery.

quant-ph↗

arXiv2020

Parallelising the Queries in Bucket Brigade Quantum RAM

Quantum algorithms often use quantum RAMs (QRAM) for accessing information stored in a database-like manner. QRAMs have to be fast, resource efficient and fault-tolerant. The latter is often influenced by access speeds, because shorter times introduce less exposure of the stored information to noise. The total execution time of an algorithm depends on the QRAM access time which includes: 1) address translation time, and 2) effective query time. The bucket brigade QRAMs were proposed to achieve faster addressing at the cost of exponentially many ancillae. We illustrate a systematic method to significantly reduce the effective query time by using Clifford+T gate parallelism. The method does not introduce any ancillae qubits. Our parallelisation method is compatible with the surface code quantum error correction. We show that parallelisation is a result of advantageous Toffoli gate decomposition in terms of Clifford+T gates, and after addresses have been translated, we achieve theoretical $\mathcal{O}(1)$ parallelism for the effective queries. We conclude that, in theory: 1) fault-tolerant bucket brigade quantum RAM queries can be performed approximately with the speed of classical RAM; 2) the exponentially many ancillae from the bucket brigade addressing scheme are a trade-off cost for achieving exponential query speedup compared to quantum read-only memories whose queries are sequential by design. The methods to compile, parallelise and analyse the presented QRAM circuits were implemented in software which is available online.

quant-ph↗

arXiv2020

QUANTIFY: A framework for resource analysis and design verification of quantum circuits

Quantum resource analysis is crucial for designing quantum circuits as well as assessing the viability of arbitrary (error-corrected) quantum computations. To this end, we introduce QUANTIFY, which is an open-source framework for the quantitative analysis of quantum circuits. It is based on Google Cirq and is developed with Clifford+T circuits in mind, and it includes the necessary methods to handle Toffoli+H and more generalised controlled quantum gates, too. Key features of QUANTIFY include: (1) analysis and optimisation methods which are compatible with the surface code, (2) choice between different automated (mixed polarity) Toffoli gate decompositions, (3) semi-automatic quantum circuit rewriting and quantum gate insertion methods that take into account known gate commutation rules, and (4) novel optimiser types that can be combined with different verification methods (e.g. truth table or circuit invariants like number of wires). For benchmarking purposes QUANTIFY includes quantum memory and quantum arithmetic circuits. Experimental results show that the framework's performance scales to circuits with thousands of qubits.

quant-ph↗

arXiv2019

Skyrmion Logic System for Large-Scale Reversible Computation

Computational reversibility is necessary for quantum computation and inspires the development of computing systems in which information carriers are conserved as they flow through a circuit. While conservative logic provides an exciting vision for reversible computing with no energy dissipation, the large dimensions of information carriers in previous realizations detract from the system efficiency, and nanoscale conservative logic remains elusive. We therefore propose a non-volatile reversible computing system in which the information carriers are magnetic skyrmions, topologically-stable magnetic whirls. These nanoscale quasiparticles interact with one another via the spin-Hall and skyrmion-Hall effects as they propagate through ferromagnetic nanowires structured to form cascaded conservative logic gates. These logic gates can be directly cascaded in large-scale systems that perform complex logic functions, with signal integrity provided by clocked synchronization structures. The feasibility of the proposed system is demonstrated through micromagnetic simulations of Boolean logic gates, a Fredkin gate, and a cascaded full adder. As skyrmions can be transported in a pipelined and non-volatile manner at room temperature without the motion of any physical particles, this skyrmion logic system has the potential to deliver scalable high-speed low-power reversible Boolean and quantum computing.

cond-mat.mes-hall↗

arXiv2019

Clifford Gate Optimisation and T Gate Scheduling: Using Queueing Models for Topological Assemblies

Clifford gates play a role in the optimisation of Clifford+T circuits. Reducing the count and the depth of Clifford gates, as well as the optimal scheduling of T gates, influence the hardware and the time costs of executing quantum circuits. This work focuses on circuits protected by the surface quantum error-correcting code. The result of compiling a quantum circuit for the surface code is called a topological assembly. We use queuing theory to model a part of the compiled assemblies, evaluate the models, and make the empiric observation that at least for certain Clifford+T circuits (e.g. adders), the assembly's execution time does not increase when the available hardware is restricted. This is an interesting property, because it shows that T gate scheduling and Clifford gate optimisation have the potential to save both hardware and execution time.

quant-ph↗

arXiv2019

Time versus Hardware: Reducing Qubit Counts with a (Surface Code) Data Bus

We introduce a data bus, for reducing the qubit counts within quantum computations (protected by surface codes). For general computations, an automated trade-off analysis (software tool and source code are open sourced and available online) is performed to determine to what degree qubit counts are reduced by the data bus: is the time penalty worth the qubit count reductions? We provide two examples where the qubit counts are convincingly reduced: 1) interaction of two surface code patches on NISQ machines with 28 and 68 qubits, and 2) very large-scale circuits with a structure similar to state-of-the-art quantum chemistry circuits. The data bus has the potential to transform all layers of the quantum computing stack (e.g., as envisioned by Google, IBM, Riggeti, Intel), because it simplifies quantum computation layouts, hardware architectures and introduces lower qubits counts at the expense of a reasonable time penalty.

quant-ph↗

arXiv2019

Universal quantum computing with thermal state bosonic systems

Recent development of mixed-state encoding (MSE) allows pure-state logical information to be encoded by a bosonic (continuous-variable) system in mixed physical state. Despite interest due to its counter-intuitiveness, the utility of the current MSE scheme is limited due to several operational drawbacks, namely redundant information carrier, probabilistic initialisation, and requirement of discrete-variable measurement. In this work, we present a simplified MSE that does not suffer from any of these drawbacks. Specifically, our protocol encodes each qubit by only one mixed-state bosonic mode, and the logical basis can be deterministically initialised from thermal equilibrium. All logical operations of this encoding can be performed with continuous-variable interaction and measurement only. Without the necessity of ground state cooling, our proposal could broaden the set of candidate systems for implementing quantum computers, and reduce the reliance on demanding refrigerating facility for current quantum computing architectures. Additionally, our protocol can enhance the noise tolerance of logical qubit even if the system can be efficiently cooled.

quant-ph↗

arXiv2019

Really Small Shoe Boxes - On Realistic Quantum Resource Estimation

Reliable resource estimation and benchmarking of quantum algorithms is a critical component of the development cycle of viable quantum applications for quantum computers of all sizes. Determining critical resource bottlenecks in algorithms, especially when resource intensive error correction protocols are required, will be crucial to reduce the cost of implementing viable algorithms on actual quantum hardware.

quant-ph↗

arXiv2019

Reliable quantum circuits have defects

State of the art quantum computing architectures are founded on the decision to use scalable but faulty quantum hardware in conjunction with an efficient error correcting code capable of tolerating high error rates. The promised effect of this decision is that the first large-scale practical quantum computer is within reach. Coming to grips with the strategy and the challenges of preparing reliable executions of an arbitrary quantum computation is not difficult. Moreover, the article explains why defects are good.

quant-ph↗

arXiv2019

SurfBraid: A concept tool for preparing and resource estimating quantum circuits protected by the surface code

The first generations of quantum computers will execute fault-tolerant quantum circuits, and it is very likely that such circuits will use surface quantum error correcting codes. To the best of our knowledge, no complete design automation tool for such circuits is currently available. This is to a large extent because such circuits have three dimensional layouts (e.g. two dimensional hardware and time axis as a third dimension) and their optimisation is still ongoing research. This work introduces SurfBraid, a tool for the automatic design of surface code protected quantum circuits -- it includes a complete workflow that compiles an arbitrary quantum circuit into an intermediary Clifford+T equivalent representation which is further synthesised and optimised to surface code protected structures (for the moment, braided defects). SurfBraid is arguably the first flexible (modular structure, extensible through user provided scripts) and interactive (automatically updating the results based on user interaction, browser based) tool for such circuits. One of the prototype's methodological novelty is its capability to automatically estimate the resources necessary for executing large fault-tolerant circuits. A prototype implementation and the corresponding source code are available at https://alexandrupaler.github.io/quantjs/.

quant-ph↗

arXiv2019

On the Influence of Initial Qubit Placement During NISQ Circuit Compilation

Noisy Intermediate-Scale Quantum (NISQ) machines are not fault-tolerant, operate few qubits (currently, less than hundred), but are capable of executing interesting computations. Above the quantum supremacy threshold (approx. 60 qubits), NISQ machines are expected to be more powerful than existing classical computers. One of the most stringent problems is that computations (expressed as quantum circuits) have to be adapted (compiled) to the NISQ hardware, because the hardware does not support arbitrary interactions between the qubits. This procedure introduces additional gates (e.g. SWAP gates) into the circuits while leaving the implemented computations unchanged. Each additional gate increases the failure rate of the adapted (compiled) circuits, because the hardware and the circuits are not fault-tolerant. It is reasonable to expect that the placement influences the number of additionally introduced gates. Therefore, a combinatorial problem arises: how are circuit qubits allocated (placed) initially to the hardware qubits? The novelty of this work relies on the methodology used to investigate the influence of the initial placement. To this end, we introduce a novel heuristic and cost model to estimate the number of gates necessary to adapt a circuit to a given NISQ architecture. We implement the heuristic (source code available on github) and benchmark it using a standard compiler (e.g. from IBM Qiskit) treated as a black box. Preliminary results indicate that cost reductions of up to 10\% can be achieved for practical circuit instances on realistic NISQ architectures only by placing qubits differently than default (trivial placement).

quant-ph↗

arXiv2018

Faster manipulation of large quantum circuits using wire label reference diagrams

Large scale quantum computing is highly anticipated, and quantum circuit design automation needs to keep up with the transition from small scale to large scale problems. Methods to support fast quantum circuit manipulations (e.g.~gate replacement, wire reordering, etc.) or specific circuit analysis operations have not been considered important and have been often implemented in a naive manner thus far. For example, quantum circuits are usually represented in term of one-dimensional gate lists or as directed acyclic graphs. Although implementations for quantum circuit manipulations are often only of polynomial complexity, the sheer number of possibilities to consider with increasing scales of quantum computations make these representations highly inefficient -- constituting a serious bottleneck. At the same time, quantum circuits have structural characteristics, which allow for more specific and faster approaches. This work utilises these characteristics by introducing a dedicated representation for large quantum circuits, namely wire label reference diagrams. We apply the representation to a set of very common circuit transformations, and develop corresponding solutions which achieve orders of magnitude performance improvements for circuits which include up to 80 000 qubits and 200 000 gates. The implementation of the proposed method is available online.

quant-ph↗

arXiv2018

Encoding Electronic Spectra in Quantum Circuits with Linear T Complexity

We construct quantum circuits which exactly encode the spectra of correlated electron models up to errors from rotation synthesis. By invoking these circuits as oracles within the recently introduced "qubitization" framework, one can use quantum phase estimation to sample states in the Hamiltonian eigenbasis with optimal query complexity $O(λ/ ε)$ where $λ$ is an absolute sum of Hamiltonian coefficients and $ε$ is target precision. For both the Hubbard model and electronic structure Hamiltonian in a second quantized basis diagonalizing the Coulomb operator, our circuits have T gate complexity $O({N + \log (1/ε}))$ where $N$ is number of orbitals in the basis. This enables sampling in the eigenbasis of electronic structure Hamiltonians with T complexity $O(N^3 /ε+ N^2 \log(1/ε)/ε)$. Compared to prior approaches, our algorithms are asymptotically more efficient in gate complexity and require fewer T gates near the classically intractable regime. Compiling to surface code fault-tolerant gates and assuming per gate error rates of one part in a thousand reveals that one can error correct phase estimation on interesting instances of these problems beyond the current capabilities of classical methods using only about a million superconducting qubits in a matter of hours.

quant-ph↗

arXiv2018

A Specification Format and a Verification Method of Fault-Tolerant Quantum Circuits

Quantum computations are expressed in general as quantum circuits, which are specified by ordered lists of quantum gates. The resulting specifications are used during the optimisation and execution of the expressed computations. However, the specification format makes it difficult to verify that optimised or executed computations still conform to the initial gate list specifications: showing the computational equivalence between two quantum circuits expressed by different lists of quantum gates is exponentially complex in the worst case. In order to solve this issue, this work presents a derivation of the specification format tailored specifically for fault-tolerant quantum circuits. The circuits are considered a form consisting entirely of single qubit initialisations, CNOT gates and single qubit measurements (ICM form). This format allows, under certain assumptions, to efficiently verify optimised (or implemented) computations. Two verification methods based on checking stabiliser circuit structures are presented.

quant-ph↗

arXiv2018

A local and scalable lattice renormalization method for ballistic quantum computation

A recent proposal has shown that it is possible to perform linear-optics quantum computation using a ballistic generation of the lattice. Yet, due to the probabilistic generation of its cluster state, it is not possible to use the fault-tolerant Raussendorf lattice, which requires a lower failure rate during the entanglement-generation process. Previous work in this area showed proof-of-principle linear-optics quantum computation, while this paper presents an approach to it which is more practical, satisfying several key constraints. We develop a classical measurement scheme, that purifies a large faulty lattice to a smaller lattice with entanglement faults below threshold. A single application of this method can reduce the entanglement error rate to $7\%$ for an input failure rate of $25\%$. Thus, we can show that it is possible to achieve fault tolerance for ballistic methods.

quant-ph↗

arXiv2018

Controlling distilleries in fault-tolerant quantum circuits: problem statement and analysis towards a solution

The failure susceptibility of the quantum hardware will force quantum computers to execute fault-tolerant quantum circuits. These circuits are based on quantum error correcting codes, and there is increasing evidence that one of the most practical choices is the surface code. Design methodologies of surface code based quantum circuits were focused on the layout of such circuits without emphasizing the reduced availability of hardware and its effect on the execution time. Circuit layout has not been investigated for practical scenarios, and the problem presented herein was neglected until now. For achieving fault-tolerance and implementing surface code based computations, a significant amount of computing resources (hardware and time) are necessary for preparing special quantum states in a procedure called distillation. This work introduces the problem of how distilleries (circuit portions responsible for state distillation) influence the layout of surface code protected quantum circuits, and analyses the trade-offs for reducing the resources necessary for executing the circuits. A first algorithmic solution is presented, implemented and evaluated for addition quantum circuits.

quant-ph↗