arXiv subjects

Ali A. Orouji

Publications and source records attributed to Ali A. Orouji.

5 recordsLinked to original sources

arXiv2019

Reversible Gates in Emerging Quantum-dot Cellular Automata Technology: An Innovative Approach to Design and Simulation

Power dissipation is known as the most notable limiting factor in all nano-electronic design techniques including Quantum-dot Cellular Automata (QCA). The familiar reversible computing approach is used as a reasonably reliable solution, mitigating power dissipation. This study presents, a comprehensive multi-objective method for designing R-Fs in emerging QCA technology. The results are investigated in both logical and layout levels, in detail. The results verify that the approach offered in this study has advantage over the most efficient approaches available in the literature by far. This comparison can be made on various parameters ranging from area, complexity (cell amount), delay (clocking zones), and to even logical levels including levels, Control inputs, the number of majority and NOT gates.

cs.ET↗

arXiv2018

New Symmetric and Planar Designs of Reversible Full-Adders/Subtractors in Quantum-Dot Cellular Automata

Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies, promising alternative to CMOS technology due to faster speed, smaller size, lower power consumption, higher scale integration and higher switching frequency. Also, power dissipation is the main limitation of all the nano electronics design techniques including the QCA. Researchers have proposed the various mechanisms to limit this problem. Among them, reversible computing is considered as the reliable solution to lower the power dissipation. On the other hand, adders are fundamental circuits for most digital systems. In this paper, Innovation is divided to three sections. In the first section, a method for converting irreversible functions to a reversible one is presented. This method has advantages such as: converting of irreversible functions to reversible one directly and as optimal. So, in this method, sub-optimal methods of using of conventional reversible blocks such as Toffoli and Fredkin are not used, having of minimum number of garbage outputs and so on. Then, Using the method, two new symmetric and planar designs of reversible full-adders are presented. In the second section, a new symmetric, planar and fault tolerant five-input majority gate is proposed. Based on the designed gate, a reversible full-adder are presented. Also, for this gate, a fault-tolerant analysis is proposed. And in the third section, three new 8-bit reversible full-adder/subtractors are designed based on full-adders/subtractors proposed in the second section. The results are indicative of the outperformance of the proposed designs in comparison to the best available ones in terms of area, complexity, delay, reversible/irreversible layout, and also in logic level in terms of garbage outputs, control inputs, number of majority and NOT gates.

cs.ET↗

arXiv2016

A multi-objective synthesis methodology for majority/minority logic networks

New technologies such as Quantum-dot Cellular Automata (QCA), Single Electron Tunneling (SET), Tunneling Phase Logic (TPL) and all-spin logic (ASL) devices have been widely advocated in nanotechnology as a response to the physical limits associated with complementary metal oxide semiconductor (CMOS) technology in atomic scales. Some of their peculiar features are their smaller size, higher speed, higher switching frequency, lower power consumption, and higher scale integration. In these technologies, the majority (or minority) and inverter gates are employed for the production of the functions as this set of gates makes a universal set of Boolean primitives in these technologies. An important step in the generation of Boolean functions using the majority gate is reducing the number of involved gates. In this paper, a multi-objective synthesis methodology (with the objective priority of gate counts, gate levels and the number of inverter gates) is presented for finding the minimal number of possible majority gates in the synthesis of Boolean functions using the proposed Majority Specification Matrix (MSM) concept. Moreover, based on MSM, a synthesis flow is proposed for the synthesis of multi-output Boolean functions. To reveal the efficiency of the proposed method, it is compared with a meta-heuristic method, multi-objective Genetic Programing (GP). Besides, it is applied to synthesize MCNC benchmark circuits. The results are indicative of the outperformance of the proposed method in comparison to multi-objective GP method. Also, for the MCNC benchmark circuits, there is an average reduction of 10.5% in the number of levels as well as 16.8% and 33.5% in the number of majority and inverter gates, as compared to the best available method respectively.

cs.ET↗

arXiv2010

Nanoscale SOI-MOSFETs with Electrically Induced Source/Drain Extension: Novel attributes and Design considerations for Suppressed Short-channel Effects

Design considerations for a below 100 nm channel length SOI MOSFET with electrically induced shallow source/drain junctions are presented. Our simulation results demonstrate that the application of induced source/drain extensions to the SOI MOSFET will successfully control the SCEs and improve the breakdown voltage even for channel lengths less than 50 nm. We conclude that if the side gate length equals the main gate length, the hot electron effect diminishes optimally.

cond-mat.mes-hall↗

arXiv2010

Leakage Current Reduction Techniques in Poly-Si TFTs for Active Matrix Liquid Crystal Displays:A Comprehensive Study

This paper critically examines the leakage current reduction techniques for improving the performance of poly-Si TFTs used in active matrix liquid crystal displays. This is a first comprehensive study in literature on this topic. The review assesses important proposals to circumvent the leakage current problem in poly-Si TFTs and a short evaluation of strengths and weaknesses specific to each method is presented. Also, a new device structure called the Triple Gate poly-Si TFT (TG-TFT) is discussed. The key idea in the operation of this device is to make the dominant conduction mechanism in the channel to be controlled by the accumulation charge density modulation by the gate (ACMG) and not by the gate-induced grain barrier lowering (GIGBL). Using twodimensional and two-carrier device simulation, it is demonstrated that the TG-TFT exhibits a significantly diminished pseudo-subthreshold conduction leading to several orders of magnitude reduction in the OFF state leakage current when compared to a conventional poly-Si TFT. The reasons for the improved performance are explained.

cond-mat.mes-hall↗