arXiv subjects

Ali Bozbey

Publications and source records attributed to Ali Bozbey.

7 recordsLinked to original sources

arXiv2025

Experimental Demonstration of a Superconductor SFQ-Based ADC for High-Frequency Signal Acquisition

Superconducting quantum interference devices (SQUIDs) are among the most sensitive sensors, offering high precision through their well-defined flux-voltage characteristics. Building on this sensitivity, we designed, fabricated, and experimentally demonstrated a superconducting single flux quantum (SFQ)-based analog-to-digital converter (ADC) capable of detecting small variations in input current signals at high frequencies and converting them into SFQ pulse trains. To improve robustness and reduce errors, the design incorporates a majority circuit and two types of counters: asynchronous toggle flip-flop-based and synchronous cumulative-based, at the cryogenic stage. The counter collects the SFQ pulse train and converts it into a binary number, simplifying downstream digital readout. The circuits were implemented using the AIST CRAVITY (QuFab) HSTP process and successfully tested in our cryocooler system, validating both the design methodology and operation. This approach helps build a fully integrated system that combines digital SQUID functionality with cryogenic readout circuits on a single chip.

cond-mat.supr-con↗

arXiv2025

Time Domain Design of a Josephson Parametric Amplifier and Comparison with Input Output Theory

Quantum-limited amplifiers, such as Josephson Traveling Wave Parametric Amplifiers (JTWPAs) and Josephson Parametric Amplifiers (JPAs), are essential components in quantum computers. They amplify low-power microwave signals from qubits at the 10 mK stage before further amplification at the 4 K stage using HEMT amplifiers. In JPAs, parametric amplification is based on the nonlinear properties of Josephson Junctions. While JPAs are typically designed and analyzed using input-output theory based on quantum physics, we propose an alternative approach based on an equivalent circuit model of JPAs, implemented using open-source Josephson circuit simulators. We compare the results with those obtained from input-output theory. This method enables the use of circuit optimizers for various objective functions and significantly reduces design time compared to quantum theory-based approaches.

quant-ph↗

arXiv2023

Efficient Superconductor Arithmetic Logic Unit for Ultra-Fast Computing

We present a 4-bit Arithmetic Logic Unit (ALU) utilizing superconductor technology. The ALU serves as the central processing unit of a processor, performing crucial arithmetic and logical operations. We have adopted a bit-parallel architecture to ensure an efficient and streamlined design with minimal fanin/fanout and optimal latency. In terms of fabrication, the ALU has been fabricated using a standard commercial process. It operates at an impressive clock frequency exceeding 30 GHz while consuming a mere 4.75 mW of power, including applied reverse current, encompassing static and dynamic components. The ALU contains over 9000 Josephson junctions, with approximately 7000 JJs dedicated to wiring, delay lines, and path balancing, and it has over 18% bias margin. Designed as a co-processor, this arithmetic logic unit will work with external CMOS memory and processors via interface circuits. Thorough testing and validation of the ALU's functionality have been conducted with digital and analog simulations, and all the components were fabricated and measured within a 4K pulse-tube cryocooler. Experimental verification has confirmed the successful operation of both the arithmetic and logic units. These results have been analyzed and are presented alongside the experimental data to provide comprehensive insights into the ALU's behavior and capabilities.

cond-mat.supr-con↗

arXiv2023

Hybrid Synaptic Structure for Spiking Neural Network Realization

Neural networks and neuromorphic computing play pivotal roles in deep learning and machine vision. Due to their dissipative nature and inherent limitations, traditional semiconductor-based circuits face challenges in realizing ultra-fast and low-power neural networks. However, the spiking behavior characteristic of single flux quantum (SFQ) circuits positions them as promising candidates for spiking neural networks (SNNs). Our previous work showcased a JJ-Soma design capable of operating at tens of gigahertz while consuming only a fraction of the power compared to traditional circuits, as documented in [1]. This paper introduces a compact SFQ-based synapse design that applies positive and negative weighted inputs to the JJ-Soma. Using an RSFQ synapse empowers us to replicate the functionality of a biological neuron, a crucial step in realizing a complete SNN. The JJ-Synapse can operate at ultra-high frequencies, exhibits orders of magnitude lower power consumption than CMOS counterparts, and can be conveniently fabricated using commercial Nb processes. Furthermore, the network's flexibility enables modifications by incorporating cryo-CMOS circuits for weight value adjustments. In our endeavor, we have successfully designed, fabricated, and partially tested the JJ-Synapse within our cryocooler system. Integration with the JJ-Soma further facilitates the realization of a high-speed inference SNN.

cond-mat.supr-con↗

arXiv2022

Superconductor modulation circuits for Qubit control at microwave frequencies

Readout and control of qubits are limiting factors in scaling quantum computers. An ideal solution is to integrate energy-efficient cryogenic circuits close to the qubits to perform control and pre-processing tasks. With orders of magnitude lower power consumption and hence lower noise, Single Flux Quantum (SFQ) and Adiabatic Quantum Flux Parametron (AQFP) superconductor logic families can reach ultimate performance at cryogenic temperatures. We have created a superconductor-based on-chip function generator to control qubits. The generated signal is modulated up to tens of GHz based on the external input waveform applied to the superconductor mixer stage. This circuit works at 4.2K. A radiofrequency (RF) matching circuit transmits the signal to the ~mK stage after digital amplification and noise reduction.

quant-ph↗

arXiv2021

A Compact High Frequency Voltage Amplifier for Superconductor-Semiconductor Logic Interface

The many advantages of cryogenically-cooled Single-Flux Quantum (SFQ) circuits imply that the high speed and low voltage output signals must be amplified and interfaced with standard electronics. State-of-the-art low-noise and wide-band amplifiers are required to interface with room temperature electronics. One solution is to place preamplifiers at the cryogenic stage, which requires specific semiconductor design and fabrication. However, a more viable and energy-efficient approach is to integrate the pulsed logic circuit output stages with on-chip superconductor preamplifiers. We designed, fabricated, and tested an on-chip compact voltage multiplier integrated with the output stage of SFQ circuits to increase the voltage amplitude of SFQ pulses. The circuit is designed with the same technology as the logic circuit hence its noise level is lower, and it works at higher frequencies compared to CMOS amplifiers and due to quantized nature of it there is no added noise. The fabricated circuit has a compact size of 160 um x 320um and provides about 10 dB gain with measured 600 uV output voltage at frequencies up to ~25 GHz in simulations. By stacking more levels, over 20 dB gain at circuit level is achievable as shown in simulations. Moreover the gain of the superconductor voltage amplifier is quantized and programmable.

physics.app-ph↗

arXiv2020

Single Flux Quantum Based Ultrahigh Speed Spiking Neuromorphic Processor Architecture

Artificial neural networks inspired by brain operations can improve the possibilities of solving complex problems more efficiently. Today's computing hardware, on the other hand, is mainly based on von Neumann architecture and CMOS technology, which is inefficient at implementing neural networks. For the first time, we propose an ultrahigh speed, spiking neuromorphic processor architecture built upon single flux quantum (SFQ) based artificial neurons (JJ-Neuron). Proposed architecture has the potential to provide higher performance and power efficiency over the state of the art including CMOS, memristors and nanophotonics devices. JJ-Neuron has the ultrafast spiking capability, trainability with commodity design software even after fabrication and compatibility with commercial CMOS and SFQ foundry services. We experimentally demonstrate the soma part of the JJ-Neuron for various activation functions together with peripheral SFQ logic gates. Then, the neural network is trained for the IRIS dataset and we have shown 100% match with the results of the offline training with 1.2x${10}^{10}$ synaptic operations per second (SOPS) and 8.57x${10}^{11}$ SOPS/W performance and power efficiency, respectively. In addition, scalability for ${10}^{18}$ SOPS and ${10}^{17}$ SOPS/W is shown which is at least five orders of magnitude more efficient than the state of the art CMOS circuits and one order of magnitude more efficient than estimations of nanophotonics-based architectures.

cs.ET↗