arXiv subjects

Anbang Wu

Publications and source records attributed to Anbang Wu.

At least 19 recordsLinked to original sources

arXiv2026

Atlas: Algorithm-Hardware Co-Design for On-Device City-Scale 3D Gaussian Splatting in VR

3D Gaussian splatting (3DGS) has drawn significant attention in the architectural community recently. However, enabling city scale 3DGS on mobile VR devices remains challenging, as the memory requirement of large scale scenes far exceeds the memory capacity of today's mobile GPUs. This paper presents Atlas, an on device city scale 3DGS rendering framework that enables scalable rendering without runtime Internet access. The key insight is that although the full 3DGS model is massive, each frame only requires a small subset of Gaussians under the current pose and level of detail requirement. Based on this insight, Atlas introduces a hierarchical memory offloading mechanism that dynamically loads only necessary Gaussian data into device memory. To further improve performance, Atlas proposes temporal aware LoD search and stereo rasterization to avoid redundant computation in VR. We further show that our technique can be integrated with existing 3DGS accelerators with negligible hardware overhead. Overall, Atlas achieves 18.5x speedup over the GPU baseline and 3.9x speedup over the state of the art 3DGS accelerators, with 92.4% energy savings.

cs.AR↗

arXiv2026

A Thread-Register Decoupled GPU Execution Model for Efficient Tensor Computation

Modern GPUs increasingly integrate Tensor Cores into the execution pipeline. Although aggregate tensor throughput continues to grow, aided by an operand supply that has evolved from register-based in Ampere to redundancy-free, memory-based in Hopper and Blackwell, efficiently orchestrating the complete tensor compute pipeline for the modern AI workloads remains challenging. We identify the fundamental bottlenecks as fixed parallelism and coarse-grained scheduling, both of which are exposed by modern AI workloads that interleave diverse non-GEMM operations with GEMM. To orchestrate tensor computation efficiently, we propose FIBER, a new architecture that extends the GPU SIMT (single instruction, multiple thread) model. Its basic execution instance, the \emph{fiber}, is decoupled from private register ownership, carrying only minimal control state while accessing an SM's registers through a shared view. This enables dynamic parallelism scaling, fine-grained register-level dataflow scheduling, and offers a redundancy-free alternative for matrix operand supply. We extend the ISA, microarchitecture, and compiler to realize shared-register addressing, conflict-free operand delivery, and fiber-based program mapping. Under a typical mixed-precision LLM serving scenario, FIBER achieves a 2.25x end-to-end speedup on Ampere (1.15x for the original FP16 computation), with 1.8x and 2.09x on Hopper and Blackwell respectively, and kernel-level gains up to 2.49x.

cs.AR↗

arXiv2026

Deltoris: Enabling Real-time VLA Inference in Embodied AI via Bit-level Sparsity and Speculative Inference

Vision-language-action (VLA) models have emerged as a key component in embodied AI. Among existing approaches, diffusion-based VLA models achieve superior motion quality and generalization. However, diffusion-based VLA models are compute-intensive and must run at high control frequency, e.g., 50-200 Hz. Thus, it imposes strict latency and energy constraints on edge devices. In this work, we present Deltoris, an algorithm-hardware co-design framework for efficient diffusion-based VLA inference. First, we exploit the temporal similarity of consecutive inputs and propose a \textit{temporal-aware bit-sparsity} algorithm that computes only the differences between consecutive inputs, eliminating redundant bit-level operations. To further address the extra off-chip traffic introduced by our algorithm, we propose a \textit{speculative inference} technique, which amortizes data loading across multiple control steps. Lastly, to support these techniques, we co-design a dedicated accelerator with customized 1D systolic bit-serial PE arrays that eliminate PE workload imbalance. Our evaluation shows that Deltoris achieves up to 34.2$\times$ speedup over mobile GPUs and 6.1$\times$ over prior accelerators, while maintaining comparable accuracy.

cs.AR↗

arXiv2026

Mosaic: Towards Efficient Training of Multimodal Models with Spatial Resource Multiplexing

With the wide adoption of Multimodal Models (MMs) in real-world scenarios, it is significant to efficiently train emerging MMs that exhibit increasingly complex module architectures. For MM deployment, existing works allocate a GPU to only one MM module in a temporal-multiplexing manner; this compromises training efficiency because a single module often fails to achieve high GPU utilization. To improve GPU utilization and enable efficient MM training, we propose deploying MMs in a temporal-spatial multiplexing manner, allowing multiple MM modules to colocate on a GPU with well-controlled resource quotas. In this paper, we propose Apollo, an efficient MM training system that applies temporal-spatial multiplexing. We first develop a flexible and lightweight execution engine that supports MM training with arbitrary resource quotas, and then build a comprehensive and accurate performance model to estimate module execution time under different allocation plans. With the performance model, we further adopt effective heuristics to derive high-quality MM deployment plans efficiently. Testbed experiments confirm that Apollo effectively improves the training efficiency of popular MMs, with a training speedup of up to 1.31x.

cs.DC↗

arXiv2025

Nebula: Enable City-Scale 3D Gaussian Splatting in Virtual Reality via Collaborative Rendering and Accelerated Stereo Rasterization

3D Gaussian splatting (3DGS) has drawn significant attention in the architectural community recently. However, current architectural designs often overlook the 3DGS scalability, making them fragile for extremely large-scale 3DGS. Meanwhile, the VR bandwidth requirement makes it impossible to deliver high-fidelity and smooth VR content from the cloud. We present Nebula, a coherent acceleration framework for large-scale 3DGS collaborative rendering. Instead of streaming videos, Nebula streams intermediate results after the LoD search, reducing 1925% data communication between the cloud and the client. To further enhance the motion-to-photon experience, we introduce a temporal-aware LoD search in the cloud that tames the irregular memory access and reduces redundant data access by exploiting temporal coherence across frames. On the client side, we propose a novel stereo rasterization that enables two eyes to share most computations during the stereo rendering with bit-accurate quality. With minimal hardware augmentations, Nebula achieves 2.7$\times$ motion-to-photon speedup and reduces 1925% bandwidth over lossy video streaming.

cs.AR↗

arXiv2025

FlashFuser: Expanding the Scale of Kernel Fusion for Compute-Intensive Operators via Inter-Core Connection

The scaling of computation throughput continues to outpace improvements in memory bandwidth, making many deep learning workloads memory-bound. Kernel fusion is a key technique to alleviate this problem, but the fusion strategies of existing compilers and frameworks are limited to using local scratchpad memory. When the intermediate results exceed the limited capacity (such as FFN), the fusion fails. Although modern GPUs (like the NVIDIA H100) now incorporate an inter-core connection mechanism known as Distributed Shared Memory(DSM)--providing a larger, high-bandwidth, and low-latency on-chip memory pool--this hardware potential has yet to be exploited by software frameworks. To bridge this gap, we present FlashFuser, the first compiler framework to utilize inter-core connection for kernel fusion on modern GPUs. FlashFuser extends established fusion techniques to the DSM domain through three core contributions. First, we propose a powerful DSM-based communication abstraction that formalizes complex cluster-based data exchange patterns, such as reduce, shuffle and multiply. Second, we introduce a dataflow analyzer that generalizes loop scheduling, resource mapping, and tile selection to the distributed memory hierarchy; it determines the optimal execution order and tile sizes by quantifying data movement across memory levels. Finally, FlashFuser integrates these components into a unified search engine that employs analytical cost modeling and DSM-aware pruning strategies to efficiently discover the optimal execution plan. Our evaluation on an NVIDIA H100 GPU shows that FlashFuser reduces memory access by 58% and delivers kernel speedups of 3.3x against highly-tuned libraries and 4.1x against state-of-the-art compilers, resulting in a 1.24x end-to-end speedup.

cs.DC↗

arXiv2025

Quantum Compiler Design for Qubit Mapping and Routing: A Cross-Architectural Survey of Superconducting, Trapped-Ion, and Neutral Atom Systems

Quantum hardware development is progressing rapidly with substantial advancements achieved across leading platforms, including superconducting circuits, trapped-ion systems, and neutral atom arrays. As the pursuit of practical quantum advantage continues, efficient quantum program compilation becomes essential for transforming high-level representations of quantum algorithms into physically executable circuits. A fundamental challenge in this process is qubit mapping and gate scheduling, which play a critical role in adapting compiled circuits to the architectural constraints and physical limitations of specific quantum hardware. In this survey, we systematically review and categorize research on the qubit mapping and routing problems across the three mainstream quantum hardware platforms. We primarily explore the development of hardware-aware compilers for superconducting platforms, classifying existing methods into solver-based, heuristic-based, and machine learning-based approaches, and analyze their optimization targets, including gate count, circuit duration, fidelity, and scalability. Furthermore, we examine the evolution of trapped-ion and neutral atom devices, analyzing the distinct challenges posed by their hardware characteristics and highlighting specialized compilers tailored to these unique physical constraints. Finally, we summarize the key challenges and identify some promising opportunities for future research in quantum compiler design across these hardware platforms.

quant-ph↗

arXiv2025

MECH: Multi-Entry Communication Highway for Superconducting Quantum Chiplets

Chiplet architecture is an emerging architecture for quantum computing that could significantly increase qubit resources with its great scalability and modularity. However, as the computing scale increases, communication between qubits would become a more severe bottleneck due to the long routing distances. In this paper, we propose a multi-entry communication highway (MECH) mechanism to trade ancillary qubits for program concurrency, and build a compilation framework to efficiently manage and utilize the highway resources. Our evaluation shows that this framework significantly outperforms the baseline approach in both the circuit depth and the number of operations on typical quantum benchmarks. This implies a more efficient and less error-prone compilation of quantum programs.

quant-ph↗

arXiv2025

Design the Quantum Instruction Set with the Cartan Coordinate Analysis Framework

Most quantum compiling efforts rely on standard two-qubit basis gates, such as CX and iSWAP, to implement general quantum operations. However, with the advancement of quantum architecture design, more nonstandard two-qubit gates can now be implemented and calibrated on devices. Using these nonstandard gates may improve the performance of quantum computation. Despite this potential, it remains unclear how to efficiently incorporate these nonstandard gates into the quantum instruction set to enhance quantum advantage. To address this, we propose an analytical framework that facilitates the design of quantum instruction sets based on nonstandard gates. Our approach is grounded in the KAK decomposition and an analysis of the Cartan coordinate of two-qubit operations, enabling analytical conversion between any two two-qubit operations. This framework also demonstrates the lower and upper bounds of the conversion cost, revealing the relationship between the entangling power of two-qubit instructions and their Cartan coordinates. We further develop a compiler based on the analytical framework, which reduces the unitary decomposition cost with nonstandard two-qubit instructions. Using the proposed compiler, we evaluate various options for designing a quantum instruction set based on nonstandard gates. Our experiments demonstrate the efficiency of the proposed framework in the quantum instruction set design. Compared to the state-of-the-art method that is based on the numerical search, our framework reduces the time/resource overhead of exploring the instruction set design space by thousands of times. Moreover, with the established framework, we propose feasible designs for the quantum instruction set by modeling real-world quantum processors, further promoting the quantum advantage.

quant-ph↗

arXiv2023

Enabling Full-Stack Quantum Computing with Changeable Error-Corrected Qubits

Executing quantum applications with quantum error correction (QEC) faces the gate non-universality problem imposed by the Eastin-Knill theorem. As one resource-time-efficient solution, code switching changes the encoding of logical qubits to implement universal logical gates. Unfortunately, it is still unclear how to perform full-stack fault-tolerant quantum computing (FTQC) based on the changeable logical qubit. Specifically, three critical problems remain unsolved: a) how to implement the dynamic logical qubit on hardware; b) how to determine the appropriate timing for logical qubit varying; c) how to improve the overall system performance for programs of different features. To overcome those design problems, We propose CECQ, to explore the large design space for FTQC based on changeable logical qubits. Experiments on various quantum programs demonstrate the effectiveness of CECQ.

quant-ph↗

arXiv2023

OneQ: A Compilation Framework for Photonic One-Way Quantum Computation

In this paper, we propose OneQ, the first optimizing compilation framework for one-way quantum computation towards realistic photonic quantum architectures. Unlike previous compilation efforts for solid-state qubit technologies, our innovative framework addresses a unique set of challenges in photonic quantum computing. Specifically, this includes the dynamic generation of qubits over time, the need to perform all computation through measurements instead of relying on 1-qubit and 2-qubit gates, and the fact that photons are instantaneously destroyed after measurements. As pioneers in this field, we demonstrate the vast optimization potential of photonic one-way quantum computing, showcasing the remarkable ability of OneQ to reduce computing resource requirements by orders of magnitude.

quant-ph↗

arXiv2022

AutoComm: A Framework for Enabling Efficient Communication in Distributed Quantum Programs

Distributed quantum computing (DQC) is a promising approach to extending the computational power of near-term quantum devices. However, the non-local quantum communication between quantum devices is much more expensive and error-prone than the local quantum communication within each quantum device. Previous work on the DQC communication optimization focus on optimizing the communication protocol for each individual non-local gate and then adopt quantum compilation designs which are designed for local multi-qubit gates (such as controlled-x or CX gates) in a single quantum computer. The communication patterns in distributed quantum programs are not yet well studied, leading to a far-from-optimal communication cost. In this paper, we identify burst communication, a specific qubit-node communication pattern that widely exists in many distributed programs and can be leveraged to guide communication overhead optimization. We then propose AutoComm, an automatic compiler framework to first extract the burst communication patterns from the input programs, and then optimize the communication steps of burst communication discovered. Experimental results show that our proposed AutoComm can reduce the communication resource consumption and the program latency by 75.6% and 71.4% on average, respectively.

quant-ph↗

arXiv2022

CollComm: Enabling Efficient Collective Quantum Communication Based on EPR buffering

The noisy and lengthy nature of quantum communication hinders the development of distributed quantum computing. The inefficient design of existing compilers for distributed quantum computing worsens the situation. Previous compilation frameworks couple communication hardware with the implementation of expensive remote gates. However, we discover that the efficiency of quantum communication, especially collective communication, can be significantly boosted by decoupling communication resources from remote operations, that is, the communication hardware would be used only for preparing remote entanglement, and the computational hardware, the component used to store program information, would be used for conducting remote gates. Based on the observation, we develop a compiler framework to optimize the collective communication happening in distributed quantum programs. In this framework, we decouple the communication preparation process in communication hardware from the remote gates conducted in computational hardware by buffering EPR pairs generated by communication hardware in qubits of the computational hardware. Experimental results show that the proposed framework can halve the communication cost of various distributed quantum programs, compared to state-of-the-art compilers for distributed quantum computing.

quant-ph↗

arXiv2021

QECV: Quantum Error Correction Verification

Quantum Error Correction (QEC) is essential for fault-tolerant quantum copmutation, and its implementation is a very sophisticated process involving both quantum and classical hardware. Formulating and verifying the decomposition of logical operations into physical ones is a challenge in itself. In this paper, we propose QECV, a verification framework that can efficiently verify the formal correctness of stabilizer codes, arguably the most important class of QEC codes. QECV first comes with a concise language, QECV-Lang, where stabilizers are treated as a first-class object, to represent QEC programs. Stabilizers are also used as predicates in our new assertion language, QECV-Assn, as logical and arithmetic operations of stabilizers can be naturally defined. We derive a sound quantum Hoare logic proof system with a set of inference rules for QECV to efficiently reason about the correctness of QEC programs. We demonstrate the effectiveness of QECV with both theoretical complexity analysis and in-depth case studies of two well-known stabilizer QEC codes, the repetition code and the surface code.

quant-ph↗

arXiv2021

Mapping Surface Code to Superconducting Quantum Processors

In this paper, we formally describe the three challenges of mapping surface code on superconducting devices, and present a comprehensive synthesis framework to overcome these challenges. The proposed framework consists of three optimizations. First, we adopt a geometrical method to allocate data qubits which ensures the existence of shallow syndrome extraction circuit. The proposed data qubit layout optimization reduces the overhead of syndrome extraction and serves as a good initial point for following optimizations. Second, we only use bridge qubits enclosed by data qubits and reduce the number of bridge qubits by merging short path between data qubits. The proposed bridge qubit optimization reduces the probability of bridge qubit conflicts and further minimizes the syndrome extraction overhead. Third, we propose an efficient heuristic to schedule syndrome extractions. Based on the proposed data qubit allocation, we devise a good initial schedule of syndrome extractions and further refine this schedule to minimize the total time needed by a complete surface code error detection cycle. Our experiments on mainsstream superconducting quantum architectures have demonstrated the efficiency of the proposed framework.

quant-ph↗

arXiv2021

Towards Efficient Ansatz Architecture for Variational Quantum Algorithms

Variational quantum algorithms are expected to demonstrate the advantage of quantum computing on near-term noisy quantum computers. However, training such variational quantum algorithms suffers from gradient vanishing as the size of the algorithm increases. Previous work cannot handle the gradient vanishing induced by the inevitable noise effects on realistic quantum hardware. In this paper, we propose a novel training scheme to mitigate such noise-induced gradient vanishing. We first introduce a new cost function of which the gradients are significantly augmented by employing traceless observables in truncated subspace. We then prove that the same minimum can be reached by optimizing the original cost function with the gradients from the new cost function. Experiments show that our new training scheme is highly effective for major variational quantum algorithms of various tasks.

quant-ph↗

arXiv2021

Mitigating Noise-Induced Gradient Vanishing in Variational Quantum Algorithm Training

quant-ph↗

arXiv2021

Paulihedral: A Generalized Block-Wise Compiler Optimization Framework For Quantum Simulation Kernels

The quantum simulation kernel is an important subroutine appearing as a very long gate sequence in many quantum programs. In this paper, we propose Paulihedral, a block-wise compiler framework that can deeply optimize this subroutine by exploiting high-level program structure and optimization opportunities. Paulihedral first employs a new Pauli intermediate representation that can maintain the high-level semantics and constraints in quantum simulation kernels. This naturally enables new large-scale optimizations that are hard to implement at the low gate-level. In particular, we propose two technology-independent instruction scheduling passes, and two technology-dependent code optimization passes which reconcile the circuit synthesis, gate cancellation, and qubit mapping stages of the compiler. Experimental results show that Paulihedral can outperform state-of-the-art compiler infrastructures in a wide-range of applications on both near-term superconducting quantum processors and future fault-tolerant quantum computers.

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