arXiv subjects

Andre Saraiva

Publications and source records attributed to Andre Saraiva.

At least 19 recordsLinked to original sources

arXiv2026

Machine Learning for Charge State Characterization of Isolated Double Quantum Dots

Scaling semiconductor quantum dot arrays toward fault-tolerant quantum computing requires efficient tuneup of spin qubits, a process that depends on the analysis of charge stability maps (CSMs) and remains largely manual. While machine learning has been widely applied to CSM analysis in reservoir-coupled devices, automated tuning in the increasingly important isolated-mode regime has received limited attention. In isolated-mode CSMs, charge transitions appear as near-vertical lines, making them well suited to compact, task-specific models. We present two convolutional neural networks with fewer than one million parameters, trained on CSMs collected from 32 silicon metal-oxide-semiconductor (SiMOS) double-quantum-dot devices measured at approximately 1 K using an automated cryogenic probing system. Sixteen devices were used for training and sixteen were held out to evaluate cross-device generalization against hand-labeled ground truth. CSMClassifier identifies charge instability and sensor artifacts, achieving 94% macro-averaged accuracy across three quality classes on 2,407 held-out images. ChargeLineNet localizes charge-transition lines and determines electron occupancy, achieving 95.3% exact line-count accuracy on 1,131 held-out images. Combined into a single pipeline, the models correctly determine electron occupancy for 93.8% of clean held-out images. Pre-training on synthetic images substantially improves label efficiency. Fine-tuning the pre-trained model on limited experimental data maintains over 90% accuracy, whereas training from scratch degrades significantly under the same conditions. Together, the two models occupy only 6.5 MB and process images in less than 60 ms on standard laboratory hardware, demonstrating a practical path toward scalable, automated characterization and tuneup of quantum-dot devices.

cond-mat.mes-hall↗

arXiv2026

SiMOS quantum-dot spin qubits enabled by extreme-ultraviolet lithography

The realization of large-scale silicon quantum processors requires spin qubits compatible with advanced semiconductor manufacturing technologies, demanding lithographic processes that combine nanometer-scale precision with exceptional uniformity. Although the highest-performing silicon spin qubits demonstrated to date have relied on electron-beam (e-beam) lithography, its serial exposure process limits reproducibility studies and wafer-scale fabrication. Here, we demonstrate high-performance silicon metal-oxide-semiconductor (SiMOS) spin qubits fabricated using extreme-ultraviolet (EUV) lithography in a 300 mm semiconductor pilot line. We report wafer-scale quantum-dot uniformity metrics, including 100 % room-temperature gate-to-gate leakage yield and sub-nanometer control of critical gate dimensions. We characterize four double-dot systems realized in two triple-quantum-dot devices. Gate set tomography (GST) reveals consistently high fidelities across all four systems, with values up to 99.8 % for SPAM, 99.9 % for single-qubit gates, and 99.1 % for two-qubit gates. The devices exhibit highly reproducible exchange turn-on characteristics of 10-13 dec/V, indicating high fabrication uniformity enabled by EUV patterning. These results establish EUV lithography as a viable manufacturing technology for quantum processors based on high-fidelity SiMOS spin qubits.

cond-mat.mes-hall↗

arXiv2026

Optimal operating temperature for industry-compatible silicon spin quantum computing: colder is not necessarily better

Silicon spin qubits are a leading candidate for large-scale quantum computing owing to their compatibility with semiconductor manufacturing. However, scaling to useful fault-tolerant processors will likely generate thermal loads that exceed the cooling power available at millikelvin temperatures. Raising the operating temperature eases cooling requirements but reduces gate fidelity, increasing the overhead of quantum error correction. Identifying the operating temperature that minimizes total power consumption is therefore a key challenge for commercially viable quantum computers. Here, we use gate set tomography to benchmark two-qubit silicon chips fabricated in both industrial and academic environments over a range of temperatures. Elevated temperatures substantially shorten coherence times and increase gate and state-preparation-and-measurement infidelities. Based on these measurements, we develop a general power model for silicon quantum computers that combines cryogenic cooling requirements with error-correction overheads. We show that a finite optimal operating temperature exists and is strongly influenced by a crossover temperature near 1 K in current devices, above which gate fidelity degrades rapidly. These results connect device-level fidelity limitations to system-level power requirements, providing design guidelines for large-scale silicon quantum computers.

quant-ph↗

arXiv2026

Multi-Qubit Entanglement of Unit Cell Pairs in SiMOS

Spin qubits in silicon-MOS (SiMOS) quantum dots have recently demonstrated compatibility with existing industry standard CMOS fabrication techniques. These devices have routinely achieved single- and two-qubit gate fidelities above 99% and demonstrated highly entangled two-qubit Bell states in isolated double quantum dot (DQD) unit cells, however coupling between unit cells has remained challenging. In this work, we present a two unit cell, four-qubit SiMOS processor with universal controllability and fully parallelised state initialisation and readout. We use this processor to generate maximally entangled three-qubit states, including the Greenberger-Horne-Zeilinger (GHZ) state, and certify multipartite entanglement through violation of the classical Mermin-witness bound. By using a fully symmetric dynamically decoupled gate sequence to create our entangled states, we are able to preserve the lifetime of the entanglement beyond $T_2^*$, to a time limited instead by $T_2^\textrm{Hahn}$. These demonstrations pave a road to the scalable operation of larger SiMOS processors, and achieving high purity, long-lived multi-qubit entangled states in them.

quant-ph↗

arXiv2026

Gate Stack Engineering for High-Mobility and Low-Noise SiMOS Quantum Devices

We systematically investigate the interplay between materials engineering, quantum transport, and low-frequency charge noise in silicon metal--oxide--semiconductor (SiMOS) quantum devices. By combining Hall-bar transport measurements with charge-noise spectroscopy of gate-defined quantum dots, we identify correlations between gate-stack design, carrier mobility, and electrostatic noise, providing an experimental case study of material and process dependencies relevant to low-noise, high-mobility operation. Hall-bar studies reveal that increasing the atomic-layer-deposition temperature of Al$_2$O$_3$ markedly enhances mobility, whereas the choice of oxidant has little impact. Devices incorporating HfO$_2$ exhibit improved carrier mobility, an interesting observation that can plausibly be attributed to defect passivation associated with aluminum diffusion from the gate metal into the HfO$_2$ layer. Charge-noise measurements show a strong correlation between higher mobility and reduced noise, with TiPd-gated devices displaying both degraded transport and elevated charge noise. In contrast, the poly-Si-gated CMOS-foundry device achieves the lowest noise levels. Finally, dual-feedback dot--sensor stability mapping demonstrates enhanced charge stability in devices with the gate stacks studied here, underscoring their promise for scalable, high-fidelity silicon spin-qubit platforms.

cond-mat.mes-hall↗

arXiv2025

OpenAI GPT-5 System Card

This is the system card published alongside the OpenAI GPT-5 launch, August 2025. GPT-5 is a unified system with a smart and fast model that answers most questions, a deeper reasoning model for harder problems, and a real-time router that quickly decides which model to use based on conversation type, complexity, tool needs, and explicit intent (for example, if you say 'think hard about this' in the prompt). The router is continuously trained on real signals, including when users switch models, preference rates for responses, and measured correctness, improving over time. Once usage limits are reached, a mini version of each model handles remaining queries. This system card focuses primarily on gpt-5-thinking and gpt-5-main, while evaluations for other models are available in the appendix. The GPT-5 system not only outperforms previous models on benchmarks and answers questions more quickly, but -- more importantly -- is more useful for real-world queries. We've made significant advances in reducing hallucinations, improving instruction following, and minimizing sycophancy, and have leveled up GPT-5's performance in three of ChatGPT's most common uses: writing, coding, and health. All of the GPT-5 models additionally feature safe-completions, our latest approach to safety training to prevent disallowed content. Similarly to ChatGPT agent, we have decided to treat gpt-5-thinking as High capability in the Biological and Chemical domain under our Preparedness Framework, activating the associated safeguards. While we do not have definitive evidence that this model could meaningfully help a novice to create severe biological harm -- our defined threshold for High capability -- we have chosen to take a precautionary approach.

cs.CL↗

arXiv2025

Mid-circuit logic executed in the qubit layer of a quantum processor

Practical quantum computers need to continuously exchange data between classical and quantum subsystems during a computation. Mid-circuit measurements of a qubits state are transferred to the classical electronics layer, and their outcome can inform feedforward operations that close the loop back to the quantum layer. These operations are crucial for fault-tolerant quantum computers, but the quantum-classical loop must be completed before the qubits decohere, presenting a substantial engineering challenge for full-scale systems comprising millions of qubits. Here we perform the first mid-circuit measurements in a system of silicon spin qubits, and show that feedforward operations can be performed without needing to route information to the classical layer. This in-layer approach leverages a backaction-driven control technique that has previously been considered a source of error. We benchmark our in-layer strategy, together with the standard FPGA-enabled approach, and analyse the performance of both methods using gate set tomography. Our results provide the first step towards moving resource-intensive classical processing into the quantum layer, an advance that could solve key engineering challenges, and drastically reduce the power budget of future quantum computers.

quant-ph↗

arXiv2025

Eight-Qubit Operation of a 300 mm SiMOS Foundry-Fabricated Device

Silicon spin qubits are a promising platform for quantum computing due to their high coherence, controllability, and CMOS manufacturability, yet scalable implementations have so far been limited to a few qubits. Here, to take a step towards larger qubit systems, we tune and coherently control an eight-dot linear array of silicon spin qubits fabricated in a 300~mm CMOS-compatible foundry process, establishing operational scalability beyond the two-qubit regime. All eight qubits are successfully tuned and characterized as four double-dot pairs, exhibiting Ramsey dephasing times $T_2^*$ up to 41(2)$~\mu$s and Hahn-echo coherence times $T_2^{\mathrm{Hahn}}$ up to 1.31(4)$~$ms. Readout of the central four qubits is achieved via a cascaded charge-sensing protocol, enabling high-fidelity measurements of the entire multi-qubit array in a two step process. Additionally, we demonstrate a two-qubit gate operation between adjacent qubits with low phase noise. We show that silicon spin qubit arrays can be scaled to medium-sized arrays of 8 qubits while maintaining system coherence.

quant-ph↗

arXiv2025

Coupling a $^{73}$Ge nuclear spin to an electrostatically defined quantum dot

Single nuclear spins in silicon are a promising resource for quantum technologies due to their long coherence times and excellent control fidelities. Qubits and qudits have been encoded on donor nuclei, with successful demonstrations of Bell states and quantum memories on the spin-1/2 $^{31}$P and cat-qubits on the spin-7/2 $^{123}$Sb nuclei. Isoelectronic nuclear spins coupled to gate-defined quantum dots, such as the naturally occurring $^{29}$Si isotope, possess no additional charge and allow for the coupled electron to be shuttled without destroying the nuclear spin coherence. Here, we demonstrate the coupling and readout of a spin-9/2 $^{73}$Ge nuclear spin to a gate-defined quantum dot in SiMOS. The $^{73}$Ge nucleus was implanted by isotope-selective ion-implantation. We observe the hyperfine interaction (HFI) to the coupled quantum dot electron and are able to tune it from 180 kHz to 350 kHz, through the voltages applied to the lateral gate electrodes. This work lays the foundation for future spin control experiments on the spin-9/2 qudit as well as more advanced experiments such as entanglement distribution between distant nuclear spins or repeated weak measurements.

cond-mat.mes-hall↗

arXiv2025

Interplay of Zeeman Splitting and Tunnel Coupling in Coherent Spin Qubit Shuttling

Spin shuttling offers a promising approach for developing scalable silicon-based quantum processors by addressing the connectivity limitations of quantum dots. In this work, we demonstrate high-fidelity bucket-brigade spin shuttling in a silicon MOS device, utilizing Pauli-spin-blockade readout. We achieve an average shuttling fidelity of \SI{99.8}{\percent}. The residual shuttling error is highly sensitive to the ratio between interdot tunnel coupling and Zeeman splitting, with tuning of these parameters enabling up to a 20-fold variation in error rate. An appropriate four-level Hamiltonian model supports our findings. These results provide valuable insights for optimizing high-performance spin-shuttling systems in future quantum architectures.

cond-mat.mes-hall↗

arXiv2025

Scalable quantum current source on commercial CMOS process technology

Many quantum technologies require a precise electrical current standard that can only be achieved with expensive cryogenics, or through the secondary standards, such as resistance or voltage. Silicon-based charge pumps could provide such a standard in an inherently scalable way, through their compatibility with complementary metal-oxide-semiconductor (CMOS) fabrication methods. However, coherent quantized charge transfer has so far been demonstrated only in nanoscale devices that are custom-fabricated in academic cleanrooms or research technology foundries. Here, we show that a CMOS device manufactured with commercial 22-nm process node can be used to define a quantum current standard in the International System of Units (SI). We measure an accuracy of (1.2 +/- 0.1)E-3 A/A at 50 MHz with reference to SI voltage and resistance standards in a pumped helium system. We then propose a practical monolithic CMOS chip that incorporates one million parallel connected charge pumps along with on-chip control electronics. This chip could be operated as a table-top primary standard that can be easily integrated with CMOS electronics, generating quantum currents of up to microampere levels.

physics.app-ph↗

arXiv2025

Effect of disorder and strain on the operation of planar Ge hole spin qubits

Germanium quantum dots in strained $\text{Ge}/\text{Si}_{1-x}\text{Ge}_{x}$ heterostructures exhibit fast and coherent hole qubit control in experiments. In this work, we theoretically and numerically address the effects of random alloy disorder and gate-induced strain on the operation of planar Ge hole spin qubits. Electrical operation of hole quantum dot spin qubits is enabled by the strong Rashba spin-orbit coupling (SOC) originating from the intrinsic SOC in the Ge valence band as well as from the structural inversion asymmetry inherent in the underlying 2D hole gas. We use the atomistic valence force field (VFF) method to compute the strain due to random alloy disorder, and thermal expansion models in COMSOL Multiphysics to obtain the strain from a realistic gate-stack of planar hole quantum dot confinement. Recently, spin-orbit coupling terms $\propto k$ have been shown to be induced by strain inhomogeneity. Our hybrid approach to realistic device modeling suggests that strain inhomogeneity due to both random alloy disorder and gate-induced strain make a strong contribution to the linear-$k$ Dresselhaus spin-orbit coupling, which eventually dominates hole spin EDSR; and there exist specific in-plane orientations of the global magnetic field $\mathbf{B}$ and the microwave drive $\mathbf{\tilde{E}}_{\text{ac}}$ for maximum EDSR Rabi frequency of the hole spin qubit. The current model including strain inhomogeneity accurately predicts the EDSR Rabi frequency to be $\!\sim\!100$ MHz for typical electric and magnetic fields in experiments, which represents at least an order of magnitude improvement in accuracy over phenomenological models assuming uniform uniaxial strain. State-of-the-art atomistic tight binding calculations via nano-electronic modeling (NEMO3D) are in agreement with the $\mathbf{k}{\cdot}\mathbf{p}$ description.

cond-mat.mes-hall↗

arXiv2025

Competitive Programming with Large Reasoning Models

We show that reinforcement learning applied to large language models (LLMs) significantly boosts performance on complex coding and reasoning tasks. Additionally, we compare two general-purpose reasoning models - OpenAI o1 and an early checkpoint of o3 - with a domain-specific system, o1-ioi, which uses hand-engineered inference strategies designed for competing in the 2024 International Olympiad in Informatics (IOI). We competed live at IOI 2024 with o1-ioi and, using hand-crafted test-time strategies, placed in the 49th percentile. Under relaxed competition constraints, o1-ioi achieved a gold medal. However, when evaluating later models such as o3, we find that o3 achieves gold without hand-crafted domain-specific strategies or relaxed constraints. Our findings show that although specialized pipelines such as o1-ioi yield solid improvements, the scaled-up, general-purpose o3 model surpasses those results without relying on hand-crafted inference heuristics. Notably, o3 achieves a gold medal at the 2024 IOI and obtains a Codeforces rating on par with elite human competitors. Overall, these results indicate that scaling general-purpose reinforcement learning, rather than relying on domain-specific techniques, offers a robust path toward state-of-the-art AI in reasoning domains, such as competitive programming.

cs.LG↗

arXiv2025

Enhancement of Electric Drive in Silicon Quantum Dots with Electric Quadrupole Spin Resonance

Quantum computation with electron spin qubits requires coherent and efficient manipulation of these spins, typically accomplished through the application of alternating magnetic or electric fields for electron spin resonance (ESR). In particular, electrical driving allows us to apply localized fields on the electrons, which benefits scale-up architectures. However, we have found that Electric Dipole Spin Resonance (EDSR) is insufficient for modeling the Rabi behavior in recent experimental studies. Therefore, we propose that the electron spin is being driven by a new method of electric spin qubit control which generalizes the spin dynamics by taking into account a quadrupolar contribution of the quantum dot: electric quadrupole spin resonance (EQSR). In this work, we explore the electric quadrupole driving of a quantum dot in silicon, specifically examining the cases of 5 and 13 electron occupancies.

cond-mat.mes-hall↗

arXiv2024

OpenAI o1 System Card

The o1 model series is trained with large-scale reinforcement learning to reason using chain of thought. These advanced reasoning capabilities provide new avenues for improving the safety and robustness of our models. In particular, our models can reason about our safety policies in context when responding to potentially unsafe prompts, through deliberative alignment. This leads to state-of-the-art performance on certain benchmarks for risks such as generating illicit advice, choosing stereotyped responses, and succumbing to known jailbreaks. Training models to incorporate a chain of thought before answering has the potential to unlock substantial benefits, while also increasing potential risks that stem from heightened intelligence. Our results underscore the need for building robust alignment methods, extensively stress-testing their efficacy, and maintaining meticulous risk management protocols. This report outlines the safety work carried out for the OpenAI o1 and OpenAI o1-mini models, including safety evaluations, external red teaming, and Preparedness Framework evaluations.

cs.AI↗

arXiv2024

A 2x2 quantum dot array in silicon with fully tuneable pairwise interdot coupling

Recent advances in semiconductor spin qubits have achieved linear arrays exceeding ten qubits. Moving to two-dimensional (2D) qubit arrays is a critical next step to advance towards fault-tolerant implementations, but it poses substantial fabrication challenges, particularly because enabling control of nearest-neighbor entanglement requires the incorporation of interstitial exchange gates between quantum dots in the qubit architecture. In this work, we present a 2D array of silicon metal-oxide-semiconductor (MOS) quantum dots with tunable interdot coupling between all adjacent dots. The device is characterized at 4.2 K, where we demonstrate the formation and isolation of double-dot and triple-dot configurations. We show control of all nearest-neighbor tunnel couplings spanning up to 30 decades per volt through the interstitial exchange gates and use advanced modeling tools to estimate the exchange interactions that could be realized among qubits in this architecture. These results represent a significant step towards the development of 2D MOS quantum processors compatible with foundry manufacturing techniques.

cond-mat.mes-hall↗

arXiv2024

A 300 mm foundry silicon spin qubit unit cell exceeding 99% fidelity in all operations

Fabrication of quantum processors in advanced 300 mm wafer-scale complementary metal-oxide-semiconductor (CMOS) foundries provides a unique scaling pathway towards commercially viable quantum computing with potentially millions of qubits on a single chip. Here, we show precise qubit operation of a silicon two-qubit device made in a 300 mm semiconductor processing line. The key metrics including single- and two-qubit control fidelities exceed 99% and state preparation and measurement fidelity exceeds 99.9%, as evidenced by gate set tomography (GST). We report coherence and lifetimes up to $T_\mathrm{2}^{\mathrm{*}} = 30.4$ $\mu$s, $T_\mathrm{2}^{\mathrm{Hahn}} = 803$ $\mu$s, and $T_1 = 6.3$ s. Crucially, the dominant operational errors originate from residual nuclear spin carrying isotopes, solvable with further isotopic purification, rather than charge noise arising from the dielectric environment. Our results answer the longstanding question whether the favourable properties including high-fidelity operation and long coherence times can be preserved when transitioning from a tailored academic to an industrial semiconductor fabrication technology.

cond-mat.mes-hall↗

arXiv2024

CMOS compatibility of semiconductor spin qubits

Several domains of society will be disrupted once millions of high-quality qubits can be brought together to perform fault-tolerant quantum computing (FTQC). All quantum computing hardware available today is many orders of magnitude removed from the requirements for FTQC. The intimidating challenges associated with integrating such complex systems have already been addressed by the semiconductor industry -hence many qubit makers have retrofitted their technology to be CMOS-compatible. This compatibility, however, can have varying degrees ranging from the mere ability to fabricate qubits using a silicon wafer as a substrate, all the way to the co-integration of qubits with high-yield, low-power advanced electronics to control these qubits. Extrapolating the evolution of quantum processors to future systems, semiconductor spin qubits have unique advantages in this respect, making them one of the most serious contenders for large-scale FTQC. In this review, we focus on the overlap between state-of-the-art semiconductor spin qubit systems and CMOS industry Very Large-Scale Integration (VLSI) principles. We identify the main differences in spin qubit operation, material, and system requirements compared to well-established CMOS industry practices. As key players in the field are looking to collaborate with CMOS industry partners, this review serves to accelerate R&D towards the industrial scale production of FTQC processors.

cond-mat.mes-hall↗