arXiv subjects

Andre Zambanini

Publications and source records attributed to Andre Zambanini.

7 recordsLinked to original sources

arXiv2026

OTTER - Two Transistor - One RRAM Architecture for Reliable In-Memory-Computing in 28 nm CMOS Technology

This work presents OTTER, a 28 nm CMOS platform co-integrated with TaOx-based valence-change mechanism (VCM) RRAM, demonstrating a two-transistor-one-memristive-device (2T1R) architecture for reliable in-memory computing. The 2T1R cell combines a low-drive-current (LD) transistor and a high-drive-current (HD) transistor in parallel, providing dedicated bias paths for SET programming and RESET operation, respectively. Through systematic experimental and simulated comparison of various transistor-pairing configurations using the physical compact model JART VCM Rth, design guidelines for transistor sizing are derived, establishing the minimum RESET transistor W/L required for complete RESET as a function of the SET current compliance. The 2T1R cell is further characterized under pulse-based programming, demonstrating multilevel analog conductance tuning with narrow, well separated conductance states across six programmable levels. An analog content-addressable memory (aCAM) design based on the same 2T1R cell is additionally analyzed at the circuit level, evaluating trade-offs between top- and bottom-connected RRAM comparator configurations. A hardware implementation of compute-in-memory (CIM) multiply-and-accumulate (MAC) operations is further demonstrated on a 15 x 15 2T1R crossbar array.

cs.ET↗

arXiv2026

A dual-polarization whitened-template trigger for real-time radio detection of extensive air showers

Autonomous radio stations require a first-stage trigger that rejects measured background while preserving weak extensive-air-shower pulses under tight hardware constraints. We present a dual-polarization trigger based on a 16-sample whitened pulse template evaluated continuously on the orthogonal north-south and east-west channels of an Auger Engineering Radio Array station. The template is derived from detector-folded air-shower pulses and whitened using the covariance of measured background. Responses from both polarizations are combined within a fixed timing radius and compared with a calibrated threshold. On an independent test set, the trigger reaches an efficiency of 0.97, with a 95 percent confidence interval of 0.96 to 0.98, at a frame-equivalent candidate rate of 3.39 kHz. At the same operating point, an unwhitened dual-polarization template reaches 0.41 efficiency and an amplitude trigger reaches 0.16. Efficiency remains at least 0.94 in every populated signal-to-noise bin. Replay of 159.29 ms of continuous measured background yields a score-cluster rate of 6.64 kHz, below the 71.4 kHz capacity of the downstream module. The FPGA implementation accepts one dual-polarization sample per clock, closes timing at 200 MHz, and uses 2377 lookup tables, 5330 registers, and 32 digital signal-processing blocks. Register-transfer-level simulation agrees bit for bit with the reference implementation for 400 traces. These results show that background covariance, pulse morphology, and dual-polarization consistency can be combined in a compact real-time radio trigger.

astro-ph.IM↗

arXiv2026

Hybrid neural denoising for resource-efficient near- and sub-threshold radio triggering of extensive air showers

Autonomous radio self-triggering for extensive air showers must reject variable radio-frequency interference while preserving sensitivity to weak pulses and remaining compatible with station-level edge hardware. This work presents a hybrid neural trigger in which waveform recovery and signal classification are treated as a single deployment-constrained problem. A compact convolutional denoiser maps a noisy single-channel trace to a cleaned estimate of the air-shower pulse, which is then evaluated by a compact classifier. The method is tested with measured high-interference background traces and detector-folded air-shower pulses from the Pierre Auger Offline simulation chain, with signals concentrated in the near- and sub-threshold regime. Model selection and deployment are linked through hyperparameter optimisation, quantisation-aware training, fixed-point quantisation, hls4ml firmware export, high-level synthesis, and register-transfer-level validation. The denoiser alone turns a simple peak-envelope decision into an efficient weak-pulse trigger, showing that the cleaned waveform carries trigger-relevant information beyond a final classifier score. In the full denoiser-classifier chain, the hybrid trigger improves signal-background separation and efficiency at fixed false-positive rates: at a false-positive rate of 10^-4, it retains about 41% of held-out signal traces in the weak-signal benchmark, while the classical peak-envelope trigger retains none. The cleaned waveform preserves timing and peak-amplitude structure for station-level diagnostics, feature extraction, and selective readout. The firmware meets timing on representative FPGA targets with microsecond-scale latency and compact arithmetic-resource demand. These results establish hybrid neural denoising as a practical route toward radio-only triggering for weak and inclined air-shower signals in noisy environments.

astro-ph.IM↗

arXiv2025

Quantization Effects of Artificial Neural Networks for Embedded Edge-Computing Applications

This paper examines the use of Quantized Neural Networks (QNNs) for two resource-constrained scientific applications: automated calibration of semi- conductor quantum bits (qubits) and scientific particle detectors. We evaluate the trade-offs between Post-Training Quantization (PTQ), Quantization-Aware Train- ing (QAT), and ultra-low-bit Binary Neural Networks (BNNs) with respect to la- tency and resource usage. Our results demonstrate that PTQ and QAT are easily implementable solutions achieving a four-fold reduction in memory usage for U- shaped CNN (U-Net) architectures, whereas BNNs are better suitable for use cases with challenging latency requirements. For the training of non-differentiable custom BNNs , we propose a novel, hardware-constrained learning approach using Genetic Algorithms (GAs). We showcase a Look-Up Table (LUT)-based BNN architecture suitable for direct conversion to Very High-Speed Integrated Circuit Hardware De- scription Language (VHDL) via the HCL4BNN framework. This method achieves nanosecond-scale inference latencies at 10 ns to 15 ns without requiring specialized Digital Signal Processor (DSP) or Block RAM (BRAM) resources.

cs.NE↗

arXiv2025

Concept of a System-on-Chip Research Platform Benchmarking Interaction of Memristor-based Bio-inspired Computing Paradigms

A system architecture is suggested for a System on Chip that will combine several different memristor-based, bio-inspired computation arrays with inter- and intra-chip communication. It will serve as a benchmark system for future developments. The architecture takes the special requirements into account which are caused by the memristor co-integration on commercial CMOS structures in a post processing step of the chip. The interface considers the necessary data bandwidth to monitor the internal Network on Chip at speed and provides enough flexibility to give different measurement options.

cs.ET↗

arXiv2023

Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array

Memristor-aided logic (MAGIC) design style holds a high promise for realizing digital logic-in-memory functionality. The ability to implement a specific gate in a MAGIC design style hinges on the SET-to-RESET threshold ratio. The TaOx memristive devices exhibit distinct SET-to-RESET ratios, enabling the implementation of OR and NOT operations. As the adoption of the MAGIC design style gains momentum, it becomes crucial to understand the breakdown of energy consumption in the various phases of its operation. This paper presents experimental demonstrations of the OR and NOT gates on a 1T1R crossbar array. Additionally, it provides insights into the energy distribution for performing these operations at different stages. Through our experiments across different gates, we found that the energy consumption is dominated by initialization in the MAGIC design style. The energy split-up is 14.8%, 85%, and 0.2% for execution, initialization, and read operations respectively.

cs.ET↗

arXiv2022

Potential for a precision measurement of solar $pp$ neutrinos in the Serappis Experiment

The Serappis (SEarch for RAre PP-neutrinos In Scintillator) project aims at a precision measurement of the flux of solar $pp$ neutrinos on the few-percent level. Such a measurement will be a relevant contribution to the study of solar neutrino oscillation parameters and a sensitive test of the solar luminosity constraint. The concept of Serappis relies on a small organic liquid scintillator detector ($\sim$20 m$^3$) with excellent energy resolution ($\sim$2.5 % at 1 MeV), low internal background and sufficient shielding from surrounding radioactivity. This can be achieved by a minor upgrade of the OSIRIS facility at the site of the JUNO neutrino experiment in southern China. To go substantially beyond current accuracy levels for the $pp$ flux, an organic scintillator with ultra-low $^{14}$C levels (below $10^{-18}$) is required. The existing OSIRIS detector and JUNO infrastructure will be instrumental in identifying suitable scintillator materials, offering a unique chance for a low-budget high-precision measurement of a fundamental property of our Sun that will be otherwise hard to access.

physics.ins-det↗