arXiv subjects

Andreas Wild

Publications and source records attributed to Andreas Wild.

9 recordsLinked to original sources

arXiv2025

Online Continual Learning on Intel Loihi 2 via a Co-designed Spiking Neural Network

AI systems on edge devices require online continual learning -- adapting to non-stationary streams and unfamiliar classes without catastrophic forgetting -- under strict power constraints. We present CLP-SNN, a spiking neural network with a self-normalizing local learning rule and a spike-driven neural state machine for autonomous on-chip learning, implemented on Intel's Loihi 2 neuromorphic processor. On OpenLORIS few-shot experiments, CLP-SNN matches replay-based accuracy rehearsal-free. On Loihi 2, CLP-SNN achieves 113x lower latency (0.33 ms vs. 37.3 ms) and 6,600x lower energy (0.05 mJ vs. 333 mJ) than the strongest edge-GPU baseline. This gain decomposes into algorithmic efficiency (~14.5x latency, ~22.6x energy on the same GPU) and neuromorphic hardware co-design (~7.8x latency, ~295x energy) exploiting event-driven learning and sparse graded-spike communication. We show that co-designed brain-inspired algorithms and neuromorphic hardware can break traditional accuracy-efficiency trade-offs in edge AI.

cs.LG↗

arXiv2025

Accelerating Linear Recurrent Neural Networks for the Edge with Unstructured Sparsity

Linear recurrent neural networks enable powerful long-range sequence modeling with constant memory usage and time-per-token during inference. These architectures hold promise for streaming applications at the edge, but deployment in resource-constrained environments requires hardware-aware optimizations to minimize latency and energy consumption. Unstructured sparsity offers a compelling solution, enabling substantial reductions in compute and memory requirements--when accelerated by compatible hardware platforms. In this paper, we conduct a scaling study to investigate the Pareto front of performance and efficiency across inference compute budgets. We find that highly sparse linear RNNs consistently achieve better efficiency-performance trade-offs than dense baselines, with 2x less compute and 36% less memory at iso-accuracy. Our models achieve state-of-the-art results on a real-time streaming task for audio denoising. By quantizing our sparse models to fixed-point arithmetic and deploying them on the Intel Loihi 2 neuromorphic chip for real-time processing, we translate model compression into tangible gains of 42x lower latency and 149x lower energy consumption compared to a dense model on an edge GPU. Our findings showcase the transformative potential of unstructured sparsity, paving the way for highly efficient recurrent neural networks in real-world, resource-constrained environments.

cs.LG↗

arXiv2024

Solving QUBO on the Loihi 2 Neuromorphic Processor

In this article, we describe an algorithm for solving Quadratic Unconstrained Binary Optimization problems on the Intel Loihi 2 neuromorphic processor. The solver is based on a hardware-aware fine-grained parallel simulated annealing algorithm developed for Intel's neuromorphic research chip Loihi 2. Preliminary results show that our approach can generate feasible solutions in as little as 1 ms and up to 37x more energy efficient compared to two baseline solvers running on a CPU. These advantages could be especially relevant for size-, weight-, and power-constrained edge computing applications.

cs.NE↗

arXiv2024

Neuromorphic quadratic programming for efficient and scalable model predictive control

Applications in robotics or other size-, weight- and power-constrained autonomous systems at the edge often require real-time and low-energy solutions to large optimization problems. Event-based and memory-integrated neuromorphic architectures promise to solve such optimization problems with superior energy efficiency and performance compared to conventional von Neumann architectures. Here, we present a method to solve convex continuous optimization problems with quadratic cost functions and linear constraints on Intel's scalable neuromorphic research chip Loihi 2. When applied to model predictive control (MPC) problems for the quadruped robotic platform ANYmal, this method achieves over two orders of magnitude reduction in combined energy-delay product compared to the state-of-the-art solver, OSQP, on (edge) CPUs and GPUs with solution times under ten milliseconds for various problem sizes. These results demonstrate the benefit of non-von-Neumann architectures for robotic control applications.

cs.NE↗

arXiv2021

A Long Short-Term Memory for AI Applications in Spike-based Neuromorphic Hardware

Spike-based neuromorphic hardware holds the promise to provide more energy efficient implementations of Deep Neural Networks (DNNs) than standard hardware such as GPUs. But this requires to understand how DNNs can be emulated in an event-based sparse firing regime, since otherwise the energy-advantage gets lost. In particular, DNNs that solve sequence processing tasks typically employ Long Short-Term Memory (LSTM) units that are hard to emulate with few spikes. We show that a facet of many biological neurons, slow after-hyperpolarizing (AHP) currents after each spike, provides an efficient solution. AHP-currents can easily be implemented in neuromorphic hardware that supports multi-compartment neuron models, such as Intel's Loihi chip. Filter approximation theory explains why AHP-neurons can emulate the function of LSTM units. This yields a highly energy-efficient approach to time series classification. Furthermore it provides the basis for implementing with very sparse firing an important class of large DNNs that extract relations between words and sentences in a text in order to answer questions about the text.

cs.NE↗

arXiv2021

NxTF: An API and Compiler for Deep Spiking Neural Networks on Intel Loihi

Spiking Neural Networks (SNNs) are a promising paradigm for efficient event-driven processing of spatio-temporally sparse data streams. SNNs have inspired the design and can take advantage of the emerging class of neuromorphic processors like Intel Loihi. These novel hardware architectures expose a variety of constraints that affect firmware, compiler and algorithm development alike. To enable rapid and flexible development of SNN algorithms on Loihi, we developed NxTF: a programming interface derived from Keras and compiler optimized for mapping deep convolutional SNNs to the multi-core Intel Loihi architecture. We evaluate NxTF on DNNs trained directly on spikes as well as models converted from traditional DNNs, processing both sparse event-based and dense frame-based data sets. Further, we assess the effectiveness of the compiler to distribute models across a large number of cores and to compress models by exploiting Loihi's weight sharing features. Finally, we evaluate model accuracy, energy and time to solution compared to other architectures. The compiler achieves near optimal resource utilization of 80% across 16 Loihi chips for a 28-layer, 4M parameter MobileNet model with input size 128x128. In addition, we report the lowest error rate of 8.52% for the CIFAR-10 dataset on neuromorphic hardware, using an off-the-shelf MobileNet.

cs.ET↗

arXiv2020

Neuromorphic Nearest-Neighbor Search Using Intel's Pohoiki Springs

Neuromorphic computing applies insights from neuroscience to uncover innovations in computing technology. In the brain, billions of interconnected neurons perform rapid computations at extremely low energy levels by leveraging properties that are foreign to conventional computing systems, such as temporal spiking codes and finely parallelized processing units integrating both memory and computation. Here, we showcase the Pohoiki Springs neuromorphic system, a mesh of 768 interconnected Loihi chips that collectively implement 100 million spiking neurons in silicon. We demonstrate a scalable approximate k-nearest neighbor (k-NN) algorithm for searching large databases that exploits neuromorphic principles. Compared to state-of-the-art conventional CPU-based implementations, we achieve superior latency, index build time, and energy efficiency when evaluated on several standard datasets containing over 1 million high-dimensional patterns. Further, the system supports adding new data points to the indexed database online in O(1) time unlike all but brute force conventional k-NN implementations.

cs.NE↗

arXiv2014

Cubic Rashba spin-orbit interaction of two-dimensional hole gas in strained-Ge/SiGe quantum well

The spin-orbit interaction (SOI) of the two-dimensional hole gas in the inversion symmetric semiconductor Ge is studied in a strained-Ge/SiGe quantum well structure. We observed weak anti-localization (WAL) in the magnetoconductivity measurement, revealing that the WAL feature can be fully described by the k-cubic Rashba SOI theory. Furthermore, we demonstrated electric field control of the Rashba SOI. Our findings reveal that the heavy hole (HH) in strained-Ge is a purely cubic-Rashba-system, which is consistent with the spin angular momentum mj = +-3/2 nature of the HH wave function.

cond-mat.mes-hall↗

arXiv2012

Few electron double quantum dot in an isotopically purified $^{28}$Si quantum well

We present a few electron double quantum dot (QD) device defined in an isotopically purified $^{28}$Si quantum well (QW). An electron mobility of $5.5 \cdot 10^4 cm^2(Vs)^{-1}$ is observed in the QW which is the highest mobility ever reported for a 2D electron system in $^{28}$Si. The residual concentration of $^{29}$Si nuclei in the $^{28}$Si QW is lower than $10^{3} ppm$, at the verge where the hyperfine interaction is theoretically no longer expected to dominantly limit the $T_{2}$ spin dephasing time. We also demonstrate a complete suppression of hysteretic gate behavior and charge noise using a negatively biased global top gate.

cond-mat.mes-hall↗