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Angel V Peterchev

Publications and source records attributed to Angel V Peterchev.

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Four-Transistor Four-Diode (4T4D) Series/Parallel Chopper Module for Auto-Balancing STATCOM and Low Control and Development Complexity

Static synchronous compensators (STATCOMs) manage reactive power compensation in modern power grids and have become essential for the integration of renewable energy sources such as wind farms. Cascaded H bridges have become the preferred topology for high-power STATCOMs, but balancing module capacitor voltages remains a persistent challenge. Conventional solutions equip every module with a voltage sensor -- a component that is costly, temperature-sensitive, and prone to aging-related failures. Recent parallel-capable module topologies can balance voltage through switched-capacitor operation. The latest developments reduced the sensor requirement from one per module to one per arm. However, these implementations require twice as many individual transistors compared to series-only topologies. We present a STATCOM solution based on the four-transistor four-diode (4T4D) series\,/\,parallel chopper cell. This topology achieves bidirectional parallelization with only four transistors per module -- exactly as many as a conventional full bridge. Furthermore, we propose a dual-loop control strategy that fully eliminates module voltage sensors by inferring voltage levels from the modulation index. This scheme also improves output quality by regulating the modulation depth. We validated our proposal through simulation and experiments. We built a prototype to interface the grid. The prototype further passed robustness tests with step change, current direction reversal, and grid disturbance. This work demonstrates the first modular STATCOM implementation that combines minimum transistor count with complete elimination of module voltage sensors.

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Conditional Nearest Level Modulation for Improved Switching Dynamics in Asymmetric Multilevel Converters

Modular multilevel converters have promising applications in clean energy, electric vehicles, and biomedical instrumentation, but need many modules to achieve fine output granularity, particularly of the voltage. Asymmetric multilevel circuits introduce differences in module voltages so that the quantity of output levels grows exponentially with the number of modules. Nearest-level modulation (NLM) is preferred over carrier-based methods in asymmetric circuits for its simplicity. However, the large number of output levels can overwhelm NLM and cause excessive transistor switching on some modules and output voltage spikes. We propose a conditional nearest-level modulation (cNLM) by incorporating mathematical penalty models to regulate switching dynamics. This approach improves output quality and reduces switching rates. Additionally, we present cNLM variations tailored for specific functions, such as enforcing a minimum switching interval. Experimental validation on an asymmetric multilevel prototype demonstrates that cNLM reduces the total output distortion from 66.3% to 15.1% while cutting the switching rate to just 8% of the original NLM.

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