arXiv subjects

Anna Wulff Christensen

Publications and source records attributed to Anna Wulff Christensen.

5 recordsLinked to original sources

arXiv2025

Roadmap to fault tolerant quantum computation using topological qubit arrays

We describe a concrete device roadmap towards a fault-tolerant quantum computing architecture based on noise-resilient, topologically protected Majorana-based qubits. Our roadmap encompasses four generations of devices: a single-qubit device that enables a measurement-based qubit benchmarking protocol; a two-qubit device that uses measurement-based braiding to perform single-qubit Clifford operations; an eight-qubit device that can be used to show an improvement of a two-qubit operation when performed on logical qubits rather than directly on physical qubits; and a topological qubit array supporting lattice surgery demonstrations on two logical qubits. Devices that enable this path require a superconductor-semiconductor heterostructure that supports a topological phase, quantum dots and coupling between those quantum dots that can create the appropriate loops for interferometric measurements, and a microwave readout system that can perform fast, low-error single-shot measurements. We describe the key design components of these qubit devices, along with the associated protocols for demonstrations of single-qubit benchmarking, Clifford gate execution, quantum error detection, and quantum error correction, which differ greatly from those in more conventional qubits. Finally, we comment on implications and advantages of this architecture for utility-scale quantum computation.

quant-ph↗

arXiv2025

Response to recent comments on Phys. Rev. B 107, 245423 (2023) and Subsection S4.3 of the Supp. Info. for Nature 638, 651-655 (2025)

The topological gap protocol (TGP) is a statistical test designed to identify a topological phase with high confidence and without human bias. It is used to determine a promising parameter regime for operating topological qubits. The protocol's key metric is the probability of incorrectly identifying a trivial region as topological, referred to as the false discovery rate (FDR). Two recent manuscripts [arXiv:2502.19560, arXiv:2503.08944] engage with the topological gap protocol and its use in Phys. Rev. B 107, 245423 (2023) and Subsection S4.3 of the Supplementary Information for Nature 638, 651-655 (2025), although they do not explicitly dispute the main results of either one. We demonstrate that the objections in arXiv:2502.19560 and arXiv:2503.08944 are unfounded, and we uphold the conclusions of Phys. Rev. B 107, 245423 (2023) and Nature 638, 651-655 (2025). Specifically, we show that no flaws have been identified in our estimate of the false discovery rate (FDR). We provide a point-by-point rebuttal of the comments in arXiv:2502.19560 and arXiv:2503.08944.

cond-mat.mes-hall↗

arXiv2024

Interferometric Single-Shot Parity Measurement in an InAs-Al Hybrid Device

The fusion of non-Abelian anyons or topological defects is a fundamental operation in measurement-only topological quantum computation. In topological superconductors, this operation amounts to a determination of the shared fermion parity of Majorana zero modes. As a step towards this, we implement a single-shot interferometric measurement of fermion parity in indium arsenide-aluminum heterostructures with a gate-defined nanowire. The interferometer is formed by tunnel-coupling the proximitized nanowire to quantum dots. The nanowire causes a state-dependent shift of these quantum dots' quantum capacitance of up to 1 fF. Our quantum capacitance measurements show flux h/2e-periodic bimodality with a signal-to-noise ratio of 1 in 3.7 $μ$s at optimal flux values. From the time traces of the quantum capacitance measurements, we extract a dwell time in the two associated states that is longer than 1 ms at in-plane magnetic fields of approximately 2 T. These results are consistent with a measurement of the fermion parity encoded in a pair of Majorana zero modes that are separated by approximately 3 $μ$m and subjected to a low rate of poisoning by non-equilibrium quasiparticles. The large capacitance shift and long poisoning time enable a parity measurement error probability of 1%.

cond-mat.mes-hall↗

arXiv2022

Doubling the mobility of InAs/InGaAs selective area grown nanowires

Selective area growth (SAG) of nanowires and networks promise a route toward scalable electronics, photonics and quantum devices based on III-V semiconductor materials. The potential of high-mobility SAG nanowires however is not yet fully realized, since interfacial roughness, misfit dislocations at the nanowire/substrate interface and non-uniform composition due to material intermixing all scatter electrons. Here, we explore SAG of highly lattice-mismatched InAs nanowires on insulating GaAs(001) substrates and address these key challenges. Atomically smooth nanowire/substrate interfaces are achieved with the use of atomic hydrogen (a-H) as an alternative to conventional thermal annealing for the native oxide removal. The problem of high lattice mismatch is addressed through an In$_x$Ga$_{1-x}$As buffer layer introduced between the InAs transport channel and the GaAs substrate. The Ga-In material intermixing observed in both the buffer layer and the channel is inhibited via careful tuning of the growth temperature. Performing scanning transmission electron microscopy and x-ray diffraction analysis along with low-temperature transport measurements we show that optimized In-rich buffer layers promote high quality InAs transport channels with the field-effect electron mobility over~10000~cm$^2$V$^{-1}$s$^{-1}$. This is twice as high as for non-optimized samples and among the highest reported for InAs selective area grown nanostructures.

cond-mat.mtrl-sci↗

arXiv2021

Selective Area Growth Rates of III-V Nanowires

Selective area growth (SAG) of semiconductors is a scalable method for fabricating gate-controlled quantum platforms. This letter reports on the adatom diffusion, incorporation, and desorption mechanisms that govern the growth rates of SAG nanowire (NW) arrays. We propose a model for the crystal growth rates that considers two parameter groups: the crystal growth control parameters and the design parameters. Using GaAs and InGaAs SAG NWs as platform we show how the design parameters such as NW pitch, width, and orientation have an impact on the growth rates. We demonstrate that by varying the control parameters (i.e. substrate temperature and beam fluxes) source, balance, and sink growth modes may exist in the SAG selectivity window. Using this model, we show that inhomogeneous growth rates can be compensated by tuning the design parameters.

cond-mat.mtrl-sci↗