arXiv subjects

Arman Ferdowsi

Publications and source records attributed to Arman Ferdowsi.

11 recordsLinked to original sources

arXiv2026

A Fault-Tolerant Spike-Time Interface for Approximate Agreement in Distributed Neuromorphic Systems

Large neuromorphic systems contain many processing tiles that may replicate a shared control parameter such as a threshold reference. If these copies diverge, identical inputs may be processed under different intended settings. We study how tiles can reduce this disagreement when communication carries only labeled spike times and up to \(f\) sender labels may be Byzantine. A raw event stream cannot supply the one-value-per-sender input required by classical approximate agreement because a faulty sender can remain silent, flood a receiver, or report different times to different receivers. We introduce the Spike-time Interface for Faults, or \SIF, which combines paced epochs, sender attribution, per-label \FirstSpike admission, bounded timing error, and a silence sentinel. For an affine one-spike code, midpoint decoding attains the exact deterministic minimax error \(\rho=\min\{1/2,\omega/L\}\), where \(\omega\) is the residual timing uncertainty and \(L\) is the usable encoding window. \SpikeTrim applies the classical mean-subsequence-reduced (MSR) rule to the sender-indexed decoded values. For \(n\ge3f+1\), it guarantees one-step robust validity, the tight noiseless contraction factor \(f/(n-2f)\) under direct updates, an explicit worst-case asymptotic disagreement bound, and finite recovery after transient agreement-state corruption. A closed-form test determines whether a validated timing budget meets a target disagreement. Simulations illustrate the fault threshold, timing dependence, flooding resistance, and recovery. A controlled spiking classifier experiment shows an association between faster control-state alignment and lower prediction disagreement under a finite maintenance budget.

cs.AR↗

arXiv2026

A Symbolic Execution Framework for Symbolic Timing Analysis of Digital Integrated Circuits

Simulation-based dynamic timing analysis of digital integrated circuits (DDTA) offers a faster alternative to traditional analog SPICE simulations. To achieve timing predictions that are reasonably competitive in terms of accuracy, however, DDTA mandates gate delay models that go beyond the standard pure or inertial delay models used in state-of-the-art tools. Recent advances in analytic gate delay models, which now also capture effects like drafting and multi-input switching, unlock new possibilities for timing analysis, which go way beyond simulation-based approaches towards an exhaustive exploration. In this paper, we present the cornerstones of a novel symbolic execution framework, which utilizes such analytic delay models for automatically computing symbolic delay expressions for all paths in a digital circuit, for some given ordering of the input transitions. To reduce combinatorial explosion, we introduce symbolic pruning methods that also enable path-sensitive, goal-driven reasoning about timing properties and analytic optimization of specific circuit paths.

cs.AR↗

arXiv2026

Certificate-Aware Property-Directed Reachability

Property-Directed Reachability (PDR/IC3) is widely used for hardware safety verification. Most implementations optimize time-to-answer, but certified workflows also require compact, inexpensive-to-check, and reproducible certificates. We introduce CAPDR, whose ranker is fitted offline on a disjoint development corpus, frozen, and used only to order PDR-generated proposals on unseen instances to target solving time, certificate size, and checker time. The ranker remains outside the trusted computing base: it cannot bypass the SAT guards on blocker insertion and pushing; obligation scheduling remains fair, and every SAFE/UNSAFE claim requires independent checker acceptance. CAPDR also defines certificate-centric metrics and replay logs for artifact-grade reproducibility. On the 2024 Hardware Model Checking Competition bit-level safety benchmarks, CAPDR solves six more instances than the same PDR engine with ranking disabled. Across each configuration's checker-accepted solved set, the medians of the certificate-size proxy and checker time decrease by 24.6% and 49%, respectively. After the same post-hoc minimizer is applied to paired SAFE outputs, CAPDR certificates still contain 16.3% fewer literals and have 38.5% lower checker time.

cs.LO↗

arXiv2025

Drafting and Multi-Input Switching in Digital Dynamic Timing Simulation for Multi-Input Gates

We present a prototype multi-input gate extension of the publicly available Involution Tool for accurate digital timing simulation and power analysis of integrated circuits introduced by Oehlinger et al. (Integration, 2021). Relying on discrete event simulation, the Involution Tool allows fast timing simulation of circuits made up of an arbitrary composition of supported gates, provides automatic random input stimulus generation, and supports parameter sweeping. It also enables a detailed comparison of the delay predictions obtained by different models, including pure and inertial delays as well as digitized SPICE-generated reference traces. Our extension added support for 2-input gates like NOR and NAND, by implementing novel analytic delay formulas obtained via a refined analysis of a recently proposed thresholded first-order hybrid model of such gates. The resulting formulas faithfully cover not only multi-input switching effects (also known as Charlie effects), but also the decay of short pulses (aka Drafting effects). Besides the fact that our analytic models not only allow the derivation of closed-form delay formulas for arbitrary compositions of such gates, they are also key for a strikingly simple procedure for model parametrization, i.e., for gate characterization, which only needs three characteristic delay values. Using the extended Involution Tool, we compare the delay and power predictions for some benchmarking circuits stimulated by randomly generated input traces. Overall, our results reveal considerably improved prediction accuracy compared to the original Involution Tool, without a noticeable performance penalty.

cs.OH↗

arXiv2025

Symbolic Timing Analysis of Digital Circuits Using Analytic Delay Functions

We propose a novel approach to symbolic timing analysis for digital integrated circuits based on recently developed analytic delay formulas for 2-input NOR, NAND, and Muller-C gates by Ferdowsi et al. (NAHS 2025). Given a fixed order of the transitions of all input and internal signals of a circuit, our framework computes closed-form analytic delay expressions for all the internal signal transition times that depend on (i) the symbolic transition times of the relevant input signals and (ii) the model parameters of the relevant gates. The resulting formulas facilitate per-transition timing analysis without any simulation, by instantiating the symbolic input transition times and the gate parameters. More importantly, however, they also enable an \emph{analytic} study of the dependencies of certain timing properties on input signals and gate parameters. For instance, differentiating a symbolic delay expression with respect to a gate parameter or input transition time enables sensitivity analysis. As a proof of concept, we implement our approach using the computer algebra system SageMath and apply it to the NOR-gate version of the c17 slack benchmark circuit.

cs.AR↗

arXiv2025

From Silicon to Spikes: System-Wide Efficiency Gains via Exact Event-Driven Training in Neuromorphic Computing

Spiking neural networks (SNNs) promise orders-of-magnitude efficiency gains by communicating with sparse, event-driven spikes rather than dense numerical activations. However, most training pipelines either rely on surrogate-gradient approximations or require dense time-step simulations, both of which conflict with the memory, bandwidth, and scheduling constraints of neuromorphic hardware and blur precise spike timing. We introduce an analytical, event-driven learning framework that computes exact gradients for synaptic weights, programmable transmission delays, and adaptive firing thresholds, three orthogonal temporal controls that jointly shape SNN accuracy and robustness. By propagating error signals only at spike events and integrating subthreshold dynamics in closed form, the method eliminates the need to store membrane-potential traces and reduces on-chip memory traffic by up to 24x in our experiments. Across multiple sequential event-stream benchmarks, the framework improves accuracy by up to 7% over a strong surrogate-gradient baseline, while sharpening spike-timing precision and enhancing resilience to injected hardware noise. These findings indicate that aligning neuron dynamics and training dynamics with event-sparse execution can simultaneously improve functional performance and resource efficiency in neuromorphic systems.

cs.NE↗

arXiv2024

Faithful Dynamic Timing Analysis of Digital Circuits Using Continuous Thresholded Mode-Switched ODEs

Thresholded hybrid systems are restricted dynamical systems, where the current mode, and hence the ODE system describing its behavior, is solely determined by externally supplied digital input signals and where the only output signals are digital ones generated by comparing an internal state variable to a threshold value. An attractive feature of such systems is easy composition, which is facilitated by their purely digital interface. A particularly promising application domain of thresholded hybrid systems is digital integrated circuits: Modern digital circuit design considers them as a composition of Millions and even Billions of elementary logic gates, like inverters, GOR and Gand. Since every such logic gate is eventually implemented as an electronic circuit, however, which exhibits a behavior that is governed by some ODE system, thresholded hybrid systems are ideally suited for making the transition from the analog to the digital world rigorous. In this paper, we prove that the mapping from digital input signals to digital output signals is continuous for a large class of thresholded hybrid systems. Moreover, we show that, under some mild conditions regarding causality, this continuity also continues to hold for arbitrary compositions, which in turn guarantees that the composition faithfully captures the analog reality. By applying our generic results to some recently developed thresholded hybrid gate models, both for single-input single-output gates like inverters and for a two-input CMOS NOR gate, we show that they are continuous. Moreover, we provide a novel thresholded hybrid model for the two-input NOR gate, which is not only continuous but also, unlike the existing one, faithfully models all multi-input switching effects.

eess.SY↗

arXiv2024

A Hybrid Delay Model for Interconnected Multi-Input Gates

Dynamic digital timing analysis is a less accurate but fast alternative to highly accurate but slow analog simulations of digital circuits. It relies on gate delay models, which allow the determination of input-to-output delays of a gate on a per-transition basis. Accurate delay models not only consider the effect of preceding output transitions here but also delay variations induced by multi-input switching (MIS) effects in the case of multi-input gates. Starting out from a first-order hybrid delay model for CMOS two-input NOR gates, we develop a hybrid delay model for Muller C gates and show how to augment these models and their analytic delay formulas by a first-order interconnect. Moreover, we conduct a systematic evaluation of the resulting modeling accuracy: Using SPICE simulations, we quantify the MIS effects on the gate delays under various wire lengths, load capacitances, and input strengths for two different CMOS technologies, comparing these results to the predictions of appropriately parameterized versions of our new gate delay models. Overall, our experimental results reveal that they capture all MIS effects with a surprisingly good accuracy despite being first-order only.

cs.AR↗

arXiv2023

An Accurate Hybrid Delay Model for Multi-Input Gates

In order to facilitate the analysis of timing relations between individual transitions in a signal trace, dynamic digital timing analysis offers a less accurate but much faster alternative to analog simulations of digital circuits. This primarily requires gate delay models that also account for the fact that the input-to-output delay of a particular input transition also depends on the temporal distance to the previous output transitions. In the case of multi-input gates, the delay also experiences variations caused by multi-input switching (MIS) effects, i.e., transitions at different inputs that occur in close temporal proximity. In this paper, we advocate the development of hybrid delay models for CMOS gates obtained by replacing transistors with time-variant resistors. We exemplify our approach by applying it to a NOR gate (and, hence, to the dual NAND gate) and a Muller C gate. We analytically solve the resulting first-order differential equations with non-constant-coefficients, and derive analytic expressions for the resulting MIS gate delays. The resulting formulas not only pave the way to a sound model parametrization procedure, but are also instrumental for implementing fast and efficient digital timing simulation. By comparison with analog simulation data, we show that our models faithfully represent all relevant MIS effects. Using an implementation in the Involution Tool, we demonstrate that our model surpasses the alternative digital delay models for NOR gates known to us in terms of accuracy, with comparably short running times.

cs.OH↗

arXiv2023

Continuity of Thresholded Mode-Switched ODEs and Digital Circuit Delay Models

Thresholded mode-switched ODEs are restricted dynamical systems that switch ODEs depending on digital input signals only, and produce a digital output signal by thresholding some internal signal. Such systems arise in recent digital circuit delay models, where the analog signals within a gate are governed by ODEs that change depending on the digital inputs. We prove the continuity of the mapping from digital input signals to digital output signals for a large class of thresholded mode-switched ODEs. This continuity property is known to be instrumental for ensuring the faithfulness of the model w.r.t. propagating short pulses. We apply our result to several instances of such digital delay models, thereby proving them to be faithful.

eess.SY↗

arXiv2021

A Simple Hybrid Model for Accurate Delay Modeling of a Multi-Input Gate

Faithfully representing small gate delay variations caused by input switchings on different inputs in close temporal proximity is a very challenging task for digital delay models. In this paper, we use the example of a 2-input NOR gate to show that a simple hybrid model leads to a surprisingly accurate digital delay model. Our model utilizes simple first-order ordinary differential equations (ODEs) in all modes, resulting from considering transistors as ideal switches in a simple RC model of the gate. By analytically solving the resulting ODEs, we derive expressions for the gate delays, as well as formulas that facilitate model parametrization. It turns out that our model almost faithfully captures the Charlie effect, except in just one specific situation. In addition, we experimentally compare our model's predictions both to SPICE simulations, using some 15 nm technology, and to some existing delay models. Our results show a significant improvement of the achievable modeling accuracy.

cs.OH↗