arXiv subjects

Arnav Shukla

Publications and source records attributed to Arnav Shukla.

2 recordsLinked to original sources

arXiv2026

Adaptive High-Speed Radar Signal Processing Architecture for 3D Localization of Multiple Targets on System on Chip

Integrated Sensing and Communication (ISAC) is a key enabler of high speed, ultra low latency vehicular communication in 6G. ISAC leverages radar signal processing (RSP) to localize multiple unknown targets amid static clutter by jointly estimating range, azimuth, and Doppler velocity (3D), thereby enabling highly directional beamforming toward intended mobile users. However, the speed and accuracy of RSP significantly impact communication throughput. This work proposes a novel 3D reconfigurable RSP accelerator, implemented on a Zynq Multi processor System on Chip (MPSoC) using a hardware software codesign approach and fixed point optimization. We propose two RSP frameworks: (1) high accuracy and high complexity, and (2) low complexity and low accuracy, along with their respective architectures. Then, we develop an adaptive architecture that dynamically switches between these two frameworks based on the signal to clutter plus noise ratio. This adaptive reconfiguration achieves up to 5.6 times faster RSP compared to state of the art designs. At the system level, the proposed RSP based ISAC delivers a 24% improvement in communication throughput without increasing hardware complexity.

eess.SP↗

arXiv2025

Taming the Tail: NoI Topology Synthesis for Mixed DL Workloads on Chiplet-Based Accelerators

Heterogeneous chiplet-based systems improve scaling by disag-gregating CPUs/GPUs and emerging technologies (HBM/DRAM).However this on-package disaggregation introduces a latency inNetwork-on-Interposer(NoI). We observe that in modern large-modelinference, parameters and activations routinely move backand forth from HBM/DRAM, injecting large, bursty flows into theinterposer. These memory-driven transfers inflate tail latency andviolate Service Level Agreements (SLAs) across k-ary n-cube base-line NoI topologies. To address this gap we introduce an InterferenceScore (IS) that quantifies worst-case slowdown under contention.We then formulate NoI synthesis as a multi-objective optimization(MOO) problem. We develop PARL (Partition-Aware ReinforcementLearner), a topology generator that balances throughput, latency,and power. PARL-generated topologies reduce contention at the memory cut, meet SLAs, and cut worst-case slowdown to 1.2 times while maintaining competitive mean throughput relative to link-rich meshes. Overall, this reframes NoI design for heterogeneouschiplet accelerators with workload-aware objectives.

cs.AR↗