arXiv subjects

Arne Loenders

Publications and source records attributed to Arne Loenders.

3 recordsLinked to original sources

arXiv2026

SiMOS quantum-dot spin qubits enabled by extreme-ultraviolet lithography

The realization of large-scale silicon quantum processors requires spin qubits compatible with advanced semiconductor manufacturing technologies, demanding lithographic processes that combine nanometer-scale precision with exceptional uniformity. Although the highest-performing silicon spin qubits demonstrated to date have relied on electron-beam (e-beam) lithography, its serial exposure process limits reproducibility studies and wafer-scale fabrication. Here, we demonstrate high-performance silicon metal-oxide-semiconductor (SiMOS) spin qubits fabricated using extreme-ultraviolet (EUV) lithography in a 300 mm semiconductor pilot line. We report wafer-scale quantum-dot uniformity metrics, including 100 % room-temperature gate-to-gate leakage yield and sub-nanometer control of critical gate dimensions. We characterize four double-dot systems realized in two triple-quantum-dot devices. Gate set tomography (GST) reveals consistently high fidelities across all four systems, with values up to 99.8 % for SPAM, 99.9 % for single-qubit gates, and 99.1 % for two-qubit gates. The devices exhibit highly reproducible exchange turn-on characteristics of 10-13 dec/V, indicating high fabrication uniformity enabled by EUV patterning. These results establish EUV lithography as a viable manufacturing technology for quantum processors based on high-fidelity SiMOS spin qubits.

cond-mat.mes-hall↗

arXiv2026

Understanding oxide-thickness-dependent variability in dense Si-MOS quantum dot arrays

Achieving uniform and scalable control of semiconductor spin qubits remains a key challenge for large scale quantum computing. In this work, we investigate how gate oxide thickness influences uniformity in dense two dimensional silicon quantum dot arrays. Using a 7 x 7 array fabricated in a 300 mm CMOS-process patterned by EUV lithography, we statistically characterize 392 quantum dots across four different oxide thicknesses. The threshold voltages, capacitances, lever arms, and charging energies are extracted using parallel row based measurements and we identify an optimal SiO2 thickness of 17 nm that minimizes threshold voltage variability below 63 mV standard deviation. Our observations illustrate how multiple sources of disorder can introduce competing oxide-thickness dependencies, resulting in non-monotonic trends. These results provide key design guidelines for dense, scalable silicon spin qubit architectures.

quant-ph↗

arXiv2024

Statistical Analysis of Spurious Dot Formation in SiMOS Single Electron Transistors

The spatial distribution of spurious dots in SiMOS single-electron transistors (SETs), fabricated on an industrial 300 mm process line, has been statistically analyzed. To have a deeper understanding of the origin of these spurious dots, we analyzed SETs with three different oxide thicknesses: 8 nm, 12 nm and 20 nm. By combining spurious dot triangulation cryo-measurement with simulations of strain, gate bias, and location of the electron wave function, we demonstrate that most spurious dots are formed through the combined effects of strain and gate bias, leading to variations in the conduction band energy. Despite the similar thermal expansion coefficients of polycrystalline silicon gates and single-crystalline silicon substrates, strain remains a crucial factor in spurious dots formation. This learning can be use to optimize the device design and the oxide thickness, to reduce the density of spurious dot while keeping quantum dot tunability.

cond-mat.mes-hall↗